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Table of contents

Overview

Key Features


  • MicroBlaze
  • LED
  • QSPI
  • UART

Revision History

DateVivadoProject BuiltAuthorsDescription
2017-12-052017.2te0803-SK0803_zusys_SDSoC-vivado_2017.1-build_05_20170911131522John Hartfielinitial release

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
No known issues---------

Requirements

Software

SoftwareVersionNote
Vivado2017.2needed
SDK2017.2needed

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0711-01-35-2C 35_2cREV01---32MB
 
TE0711-01-100-2C 100_2cREV01---32MB
 
TE0711-01-35-2I 35_2iREV01---32MB
 
TE0711-01-100-2I100_2iREV01---32MB

Design supports following carriers:

Carrier ModelNotes
TE0701
TE0703
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • Used as reference carrier.
TE0705
TE0706
TEBA0841
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI

Content

For general structure and of the reference design, see Project Delivery

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI

Additional Sources

TypeLocationNotes

Prebuilt

File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

SDSoC (only tested on Win OS)

  1. Generate Platform Project or use prebuilt from download
  2. ...

Launch

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Not used on this Example.

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root

 

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

_i_io.xdc
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - SDK/HSI

For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

Xilinx default FSBL

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};


Kernel

No changes.

Rootfs

No changes.

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

No additional software is needed.

SDSoC Design

Description currently not available.

SDSoC Platform

SDSoC Demo Examples

SDSoC platform includes 21 demo projects demonstrating optimization techniques for Standalone and Linux targets with HW acceleration or in SW for fast compilation and debug. These projects have been downloaded and installed into the SDSoC platform from https://github.com/Xilinx/SDSoC_Examples

  • array_partition
  • burst_rw
  • custom_data_type
  • data_access_random
  • dependence_inter
  • direct_connect
  • dma_sg
  • dma_simple
  • full_array_2d
  • hello_vadd
  • lmem_2rw
  • loop_fusion
  • loop_perfect
  • loop_pipeline
  • loop_reorder
  • row_array_2d
  • shift_register
  • systolic_array
  • sys_port
  • wide_memory_rw
  • window_array_2d

 

There are 3 larger Linux demo projects demonstrating video processing with data I/O from file to file. Source code of these projects have been installed into this platform from the Xilinx SDSoC 2016.4 release:

  • file_io_manr_sobel
  • file_io_optical
  • file_io_sbm

These larger Linux demo projects demonstrate video processing with data I/O from file to file. Source code of these projects have been installed into this platform from demos present in the Xilinx SDSoC 2016.4 release.

Compilation steps in the SDSoC 2017.1 is identical to above described examples. File I/O demos support only the Linux target.

These three files use as an input larger video files. These files have to be present on the SD card as an input. Algorithms write output file to the SD card. These files can be visualized by YUV Player Deluxe and other players. To reduce size of the project, the video data files are not included.

Video input files can be found in the Xilinx SDSoC 2016.4 distribution:

  • <xilinx install path>\SDx\2016.4\samples\file_io_manr_sobel\input.yuv
  • <xilinx install path>\SDx\2016.4\samples\file_io_optical\route85_1920x1080.yuv
  • <xilinx install path>\SDx\2016.4\samples\file_io_sbm\desk_1280x720.yuv

 

Array partition

This example shows how to use array partitioning to improve performance of a hardware function.

Key Concepts:

  •  Hardware Function Optimization
  •  Array Partitioning

Keywords:

  •  #pragma HLS ARRAY_PARTITION
  •  complete

Burst rw

This is a simple vector increment example which demonstrates usage of AXI4-master interface for burst read and write.

Key Concepts:

  •  Burst Access

Custom data type

This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR.

Key Concepts:

  •  Custom Data Type

Keywords:

  •  struct
  •  packed
  •  aligned

Data access random

This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern.

Key Concepts:

  •  Data Access Random

Keywords:

  •  #pragma HLS PIPELINE
  •  #pragma SDS access_pattern(a:RANDOM, b:RANDOM)
  •  #pragma SDS data copy

Dependence inter

This is a simple example to demonstrate inter dependence attribute using vertical convolution example. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance.

Key Concepts:

  •  Inter Dependence

Keywords:

  •  DEPENDENCE
  •  inter

Direct connect

This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C) to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency.

Key Concepts:

  •  Direct Connection
  •  Multiple Accelerators

Keywords:

  •  #pragma SDS data access_pattern(in1:SEQUENTIAL, in2:SEQUENTIAL, out:SEQUENTIAL)

Dma sg

This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator.

Key Concepts:

  •  Scatter Gather DMA

Keywords:

  •  #pragma SDS access_parttern(a:SEQUENTIAL)
  •  #pragma SDS data_mover(a:AXIDMA_SG)
  •  #pragma SDS data copy

Dma simple

This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator.

Key Concepts:

  • Simple DMA

Keywords:

  • #pragma SDS access_parttern(a:SEQUENTIAL)
  • #pragma SDS data_mover(a:AXIDMA_SIMPLE)
  • #pragma SDS data copy

Full array 2d

This is a simple example of accessing full data from 2D array.

Key Concepts:

  •  2D data array access

Hello vadd

----------

This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function.

Key Concepts:

  •  - Loop Pipelining

Keywords:

  •  - #pragma HLS PIPELINE

Lmem 2rw

This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory.

Key Concepts:

  •  Hardware Function Optimization
  •  2port BRAM Utilization
  •  Two read/write Local Memory

Keywords:

  •  #pragma HLS UNROLL FACTOR=2

Loop fusion

This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function.

Key Concepts:

  •  Hardware Function Optimization
  •  Loop Fusion
  •  Loop Pipelining

Keywords:

  •  #pragma HLS PIPELINE

Loop perfect

This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop.

Key Concepts:

  • Loop perfect

Keywords:

  • #pragma HLS PIPELINE
  • #pragma HLS ARRAY_PARTITION

Loop pipeline

This example demonstrates how loop pipelining can be used to improve the performance of a hardware function.

Key Concepts:

  • Loop Pipelining

Keywords:

  • #pragma HLS PIPELINE

Loop reorder

This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering.

Key Concepts:

  •  Hardware Function Optimization
  •  Loop Reorder to Improve II

Keywords:

  •  #pragma HLS PIPELINE
  •  #pragma HLS ARRAY_PARTITION

Row array 2d

This is a simple example of accessing each row of data from 2D array.

Key Concepts:

  • Row of 2D data array access

Keywords:

  • hls::stream

Shift register

This example demonstrates how to shift values in each clock cycle.

Key Concepts:

  • Hardware Function Optimization
  • Shift Register
  • FIR

Keywords:

  • #pragma HLS ARRAY_PARTITION

Systolic array

This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA.

Key Concepts:

  • Systolic Array

Keywords:

  • #pragma HLS PIPELINE
  • #pragma HLS ARRAY_PARTITION

Sys port

This is a simple example which demonstrates sys_port usage.

Key Concepts:

  • sys_port
  • memory interface
  • memory non-caching

Keywords:

  • #pragma SDS data sys_port
  • #pragms HLS PIPELINE
  • sds_alloc_non_cacheable

Wide memory rw

This is a simple example of vector addition to demonstrate Wide Memory Access using structure data type of 128bit wide. Based on input argument type, sds++ compiler will figure out the memory interface datawidth of hardware accelerator.

Key Concepts:

  • wide memory access
  • burst read and write
  • custom datatype

Keywords:

  • struct

Window array 2d

This is a simple example of accessing window of data from 2D array.

Key Concepts:

  • Window of 2D data array access

Keywords:

  • #pragma HLS DATAFLOW
  • #pragma HLS PIPELINE
  • #pragma HLS stream

File IO Video Processing

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing includes Motion Adaptive Noise Reduction (MANR) followed by a Sobel filter for edge detection. You can run it by supplying a 1080p YUV422 file as input with limiting number of frames to a maximum of 20 frames.

Key Concepts:

  • Video processing from file to file
  • Direct connection of HW accelerated blocks

 

Select the "File IO Video Processing" template an compile for Linux target as project te22. Copy result to root of SD card. Copy also the input file input.yuv (82 944 000 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by comman ./te22.elf ./input.yuv 20 3 ./output.yuv

The output.yuv file contains 20 frames of 1080p vido in YUV422 format with computed edges. Copy output.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Dense Optical Flow

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs LK Dense Optical Flow over two Full HD frames video file. You can run it by supplying a 1080p YUV422 file route85_1920x1080.yuv as input.

Key Concept:s

  • Video processing from file to file
  • Direct connection of HW accelerated blocks
  • Top down methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

 

Select the "File IO Dense Optical Flow" template an compile for Linux target as project te23. Copy result to root of SD card. Copy also the input file route85_1920x1080.yuv (8 294 400 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te23.elf

The OptFlow_1920x1080.yuv file is generated and stored on the SD card. It contains one 1080p frame in YUV422 format with computed dense optical flow vectors. Copy OptFlow_1920x1080.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Stereo Block Matching

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs Stereo Block Matching to calculate depth in a single sample stereo video file desk_1280x720.yuv in YUV422 format as input and single frame Disparity_640x720.yuv in YUV422 format as output, indicating the depth of objects.

Key Concepts:

  • Video processing from file to file
  • Bottom Up methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

 

Select the "File IO Stereo Block Matching" template an compile for Linux target as project te24. Copy result to root of SD card. Copy also the input file desk_1280x720.yuv (1 843 200 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te24.elf

The Disparity_640x720.yuv file is generated and stored on the SD card. It contains one 640x720 frame in YUV422 format indicating the depth of objects. Copy Disparity_640x720.yuv file to PC and visualise it in yuvplayer (size 640x720 colour YUV422) The input file desk_1280x720.yuv can be visualised by yuvplayer (size 1280x720 colour YUV422). It contains side by side two colour frames from a stereo camera.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

v.2



Work in progress
2017-10-19 v.21John HartfielWork in progress
2017-09-11v.1Initial release
 All 

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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