Table of contents
Overview
Example show, how to reconfigure SI5338 with MCS and monitor CLK. Additional MicroBlaze is add for Hello TE0741 example.
Key Features
- MGT
- SI5338 initialisation with MCS
Revision History
| Date | Vivado | Project Built | Authors | Description |
|---|---|---|---|---|
| 2018-06-05 | 2017.4 | TE0841-IBERT_noprebuilt-vivado_2017.4-build_10_20180605143852.zip TE0841-IBERT-vivado_2017.4-build_10_20180605143837.zip | John Hartfiel |
|
Release Notes and Know Issues
| Issues | Description | Workaround | To be fixed version |
|---|---|---|---|
| --- | --- | --- | --- |
Requirements
Software
| Software | Version | Note |
|---|---|---|
| Vivado | 2017.4 | needed |
| SDK | 2017.4 | needed |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
| Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
|---|---|---|---|---|---|---|
| TE0841-01-035-1C | 01_35_1c | REV01 | 2x 512MB DDR4 | 32MB | --- | |
| TE0841-01-035-1I | 01_35_1i | REV01 | 2x 512MB DDR4 | 32MB | --- | |
| TE0841-01-035-2I | 01_35_2i | REV01 | 2x 512MB DDR4 | 32MB | --- | |
| TE0841-01-040-1C | 01_40_1c | REV01 | 2x 512MB DDR4 | 32MB | --- | |
| TE0841-01-040-1I | 01_40_1i | REV01 | 2x 512MB DDR4 | 32MB | --- | |
| TE0841-01-040-2I | 01_40_2i | REV01 | 2x 512MB DDR4 | 32MB | --- |
Design supports following carriers:
| Carrier Model | Notes |
|---|---|
| TEBA0841 | used as reference carrier |
Additional HW Requirements:
| Additional Hardware | Notes |
|---|---|
| USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type |
| XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
| Heat sink | It's recommended to use heat sink for this design |
Content
For general structure and of the reference design, see Project Delivery
Design Sources
| Type | Location | Notes |
|---|---|---|
| Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib <design name>/firmware | Vivado Project will be generated by TE Scripts |
| SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
Additional Sources
| Type | Location | Notes |
|---|---|---|
| SI5338 Project | \misc\SI5338 |
Prebuilt
File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA (PL Part) Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:Vivado/SDK/SDSoC
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate MCS Firmware (optional):
- Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
- Create "SCU" application
Note: Select MCS Microblaze and SCU Application - Select Release Built
- Regenerate App
- (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into "\firmware\microblaze_mcs_0\"
- Regenerate Vivado Project or Update Bitfile only and "scu.elf"
- Copy MCS file with Bitfile into prebuilt folder
- Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_hsi
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp
Note: Alternative use SDK or setup Flash on Vivado manually - Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
- Connect JTAG and power on PCB
- Open Vivado HW Manager
- Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Power on PCB
Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts IBERT.
Do not reboot, if Bitfile programming over JTAG is used as programming method.- On TE0841 SI5338 has default configuration and reprogramming of SI5338 is optional
- LED:
- D1 (green) OFF→ MCS SI configuration finished (System Reset is off)
Vivado HW Manager:
- Open Vivado HW-Manager
- "Refresh device" is needed after Bitfile programming, because MCS reconfigure SI5338 and enables IBERT a little bit later.
- loopback depends on TEB0841 Revision an connection
| IBERT | Component Name | Net Name | TEB0841 |
|---|---|---|---|
| X0Y0 | 224-0 | MGT4 | loop back RX/TX |
| X0Y1 | 224-1 | MGT5 | loop back RX/TX |
| X0Y2 | 224-2 | MGT6 | loopback over SD Pin header possible with lower Linerate otherwise use internal loopback |
| X0Y3 | 224-3 | MGT7 | loop back RX/TX. Note: N.C. on TEB0841-01, use internal loopback |
| X0Y4 | 225-0 | MGT0 | loop back RX/TX |
| X0Y5 | 225-1 | MGT1 | loop back RX/TX |
| X0Y6 | 225-2 | MGT2 | loop back RX/TX |
| X0Y7 | 225-3 | MGT3 | loopback over sfp possible |
System Design - Vivado
Block Design
HDL
- IBERT_top.v
- ibert xci IPs
Constrains
Basic module constrains
_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design] set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
Design specific constrain
ibert_ultrascale_gth_0.xdc
# file: ibert_ultrascale_gth_0.xdc #################################################################################### ## ____ ____ ## / /\/ / ## /___/ \ / Vendor: Xilinx ## \ \ \/ Version : 2012.3 ## \ \ Application : IBERT Ultrascale ## / / Filename : example_ibert_ultrascale_gth_0.xdc ## /___/ /\ ## \ \ / \ ## \___\/\___\ ## ## ## ## Generated by Xilinx IBERT 7Series ##************************************************************************** ## ## Icon Constraints ## create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i] set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub] ##gth_refclk lock constraints ## set_property PACKAGE_PIN AD6 [get_ports gth_refclk0p_i[0]] set_property PACKAGE_PIN AD5 [get_ports gth_refclk0n_i[0]] set_property PACKAGE_PIN AB6 [get_ports gth_refclk1p_i[0]] set_property PACKAGE_PIN AB5 [get_ports gth_refclk1n_i[0]] ## ## Refclk constraints ## create_clock -name gth_refclk0_0 -period 8.0 [get_ports gth_refclk0p_i[0]] create_clock -name gth_refclk1_0 -period 8.0 [get_ports gth_refclk1p_i[0]] set_clock_groups -group [get_clocks gth_refclk0_0 -include_generated_clocks] -asynchronous set_clock_groups -group [get_clocks gth_refclk1_0 -include_generated_clocks] -asynchronous ## ## System clock pin locs and timing constraints ## set_property PACKAGE_PIN R25 [get_ports gth_sysclkp_i] set_property IOSTANDARD LVDS [get_ports gth_sysclkp_i]
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
Application
SCU
MCS Firmware to configure SI5338 and Reset System.
Template location: \sw_lib\sw_apps\scu
Additional Software
SI5338
Download ClockBuilder Desktop for SI5338
- Install and start ClockBuilder
- Select SI5338
- Options → Open register map file
Note: File location <design name>/misc/Si5338/RegisterMap.txt - Modify settings
- Options → save C code header files
- Replace Header files from SCU template with generated file
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
| Date | Document Revision | Authors | Description |
|---|---|---|---|
| |||
| 2018-04-16 | v.1 |
| |
| All |
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