Table of Contents
The Trenz Electronic TEI0001 is a low cost small-sized FPGA module integrating a Intel Cyclone 10LP 10CL025 FPGA SoC, 2 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.
Intel Cyclone 10LP 10CL025 FPGA SoC
- 8 MByte SDRAM
2 MByte serial configuration memory
- ST Microelectronics LIS3DH 3-axis accelerometer
- JTAG and UART over Micro USB2 connector
- 1x6 pin header for JTAG access to FPGA SoC
- 1x PMOD header providing 8 GPIOs
2x 14-pin headers (2,54 mm pitch) providing 23 GPIOs
- 1x 3-pin header providing 2 GPIOs
8x user LEDs
- 1x user push button
- 5.0V single power supply with on-board voltage regulators
- Size: 61.5 x 25 mm
Additional assembly options are available for cost or performance optimization upon request.
- Intel Cyclone 10LP 10CL025 FPGA SoC, U1
- Winbond W9864G6JT 8 Mbyte SDRAM 166MHz, U2
- Intel EPCQ16ASI8N 2 MByte serial configuration memory, U5
- ST Microelectronics LIS3DH 3-axis accelerometer, U4
- FTDI USB2 to JTAG/UART adapter, U3
- Configuration EEPROM for FTDI chip, U9
- 12.0000 MHz oscillator, U7
- 8x red user LEDs, D2 ... D9
- Red LED (Conf. DONE), D10
- Green LED (indicating supply voltage), D1
- Push button (user), S2
- Push button (reset), S1
- Micro USB2 B socket (receptacle), J9
- 1x14 pin header (2.54mm pitch), J2
- 1x6 pin header (2.54mm pitch), J4
- 2x6 Pmod connector, J6
- 3-pin header (2.54mm pitch), J3
- 1x14 pin header (2.54mm pitch), J1
Initial Delivery State
Storage device name
Serial configuration memory, U5
|I2C Configuration EEPROM, U9|
Table 1: Initial delivery state of programmable devices on the module
By default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory, hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memory.
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:
|Bank||Connector Designator||I/O Signal Count||Bank Voltage||Notes|
|2||J2||9 I/O's||3.3V||2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same bank or pins can be shared|
|6||J6||8 I/O's||3.3V||Pmod Connector|
|1||J4||4 I/O's||3.3V||JTAG interface|
|J2||1 Input||3.3V||low active Reset input|
Table 2: General overview of single ended I/O signals connected to pin headers and connectors
FPGA I/O banks
|Bank||VCCIO||I/O's Count||Connected to||Notes|
|1||3.3V||6||LIS3DH digital motion sensor, U4||SPI interface, 2 interrupt lines|
|4||1x6 pin header, J4||JTAG interface|
|4||2 MByte serial configuration memory, U5||FPGA configuration memory with active serial (AS) x1 interface|
|1||J2-10, push button S1||low active reset input|
|2||3.3V||9||1x14 pin header, J2||GPIOs (2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same Bank or pins can be shared)|
|3||3.3V||8||LEDs D2 ... D9||8 x red user LEDs|
|8||FTDI FT2232H JTAG/UART Adapter, U3||configurable as GPIO/UART or other serial interfaces|
|1||push button S2||user button|
|4||3.3V||10||pin headers J1, J3||GPIOs|
|5||3.3V||6||pin headers J1||GPIOs|
|6||3.3V||8||Pmod connector J6||GPIOs|
|1||Red LED, D10||Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)|
|7||3.3V||19||8 Mbyte SDRAM 166MHz, U2||16bit SD-RAM memory interface|
|8||3.3V||21||8 Mbyte SDRAM 166MHz, U2||16bit SD-RAM memory interface|
Table 3: General overview of FPGA I/O banks
Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.
Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:
|JTAG Signal||Pin on Header J4||Note|
Table 4: optional JTAG pin header
Serial Configuration Memory
On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.
|Serial Memory U5 Pin||Signal Schematic Name||Connected to||Notes|
|Pin 2, DATA1||AS_DATA0||FPGA bank 1, pin H2||Data out|
|Pin 5, DATA0||AS_ASDO||FPGA bank 1, pin C1||Data in|
|Pin 1, nCS||AS_NCS||FPGA bank 1, pin D2||chip select|
|Pin 6, DCLK||AS_DCLK|
FPGA bank 1, pin H1
Table 5: Serial configuration memory interface connections
The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2. This SDRAM chip is connected to the FPGA bank 7 and 8 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
|SDRAM I/O Signals|
Signal Schematic Name
A0 ... A13
|Bank address inputs|
BA0 / BA1
DQ0 ... DQ15
DQM0 ... DQM1
Row Address Strobe
Column Address Strobe
|WE||bank 8||Write Enable|
Table 6: 16bit SDRAM memory interface
FTDI FT2232H Chip
The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 2 I/O's of channel A and 6 I/O's of Channel B are routed to FPGA bank 3 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
|FTDI Chip U3 Pin||Signal Schematic Name||Connected to||Notes|
|Pin 12, ADBUS0||TCK||FPGA bank 1, pin H3||JTAG interface|
|Pin 13, ADBUS1||TDI||FPGA bank 1, pin H4|
|Pin 14, ADBUS2||TDO||FPGA bank 1, pin J4|
|Pin 15, ADBUS3||TMS|
FPGA bank 1, pin J5
|Pin 17, ADBUS4||ADBUS4||FPGA bank 3, pin M8||user configurable|
|Pin 20, ADBUS7||ADBUS7||FPGA bank 3, pin N8||user configurable|
|Pin 32, BDBUS0||BDBUS0||FPGA bank 3, pin||user configurable|
|Pin 33, BDBUS1||BDBUS1||FPGA bank 3, pin||user configurable|
|Pin 34, BDBUS2||BDBUS2||FPGA bank 3, pin||user configurable|
|Pin 35, BDBUS3||BDBUS3||FPGA bank 3, pin||user configurable|
|Pin 37, BDBUS4||BDBUS4||FPGA bank 3, pin||user configurable|
|Pin 38, BDBUS5||BDBUS5||FPGA bank 3, pin||user configurable|
Table 7: FTDI chip interfaces and pins
On the TEI0003 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.
|Accelerometer U4 Pin||Signal Schematic Name||Connected to||Notes|
|Pin 11, INT1||SEN_INT1||FPGA bank 1, pin B1||Interrupt lines|
|Pin 9, INT2||SEN_INT2||FPGA bank 1, pin C2|
|Pin 6, SDA/SDI/SDO||SEN_SDI||FPGA bank 1, pin G2||SPI interface|
|Pin 7, SDO/SA0||SEN_SDO|
FPGA bank 1, pin G1
|Pin 4, SCL/SPC||SEN_SPC||FPGA bank 1, pin F3|
|Pin 8, CS||SEN_CS||FPGA bank 1, pin D1|
|Pin 13, ADC3||ADC3||5V||Sense 5V input voltage|
Table 8: 3-axis accelerometer interfaces and pins
System Clock Oscillator
The FPGA SoC module has following reference clocking signals provided by on-board oscillators:
|Clock Source||Schematic Name||Frequency||Clock Input Destination|
|Microchip MEMS Oscillator, U7||CLK12M||12.0000 MHz||FTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin M2|
|optional Microchip MEMS Oscillator, U6 (not fitted)||CLK_X||-||FPGA SoC bank 6, pin E15|
Table 9: Clock sources overview
There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.
|LED||Color||Signal Schematic Name||FPGA||Notes|
|D1||Green||-||-||Indicating 3.3V board supply voltage|
|D2||Red||'LED1'||bank 6, pin M6||user|
|D3||Red||'LED2'||bank 6, pin T4||user|
|D4||Red||'LED3'||bank 6, pin T3||user|
|D5||Red||'LED4'||bank 6, pin R3||user|
|D6||Red||'LED5'||bank 6, pin T2||user|
|D7||Red||'LED6'||bank 6, pin R4||user|
|D8||Red||'LED7'||bank 6, pin N5||user|
|D9||Red||'LED8'||bank 6, pin N3||user|
|D10||Red||'CONF_DONE'||bank 6, pin H14||indication configuration is DONE when LED is off|
Table 10: LEDs of the module
The FPGA module is equipped with two push buttons S1 and S2:
|Button||Signal Schematic Name||FPGA||Notes|
|S1||'USER_BTN'||bank 3, pin N6||user configurable|
|S2||'RESET'||bank 1, pin H5||system reset|
Table 11: Push buttons of the module
All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.
The TEI0003 module needs one single power supply of 5.0V nominal.
There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:
|FPGA||Design||Typical Power, 25C ambient|
|Intel Cyclone 10LP 10CL025 FPGA SoC||Not configured||TBD*|
Table 12: Module power consumption
*TBD - To Be Determined.
Actual power consumption depends on the FPGA design and ambient temperature.
There is no specific or special power-on sequence, just one single power source is needed.
|Connector Designator||VCC / VCCIO Schematic Name||Voltage||Direction||Pins||Notes|
|Out||Pin 6, 12||-|
Table 13: Connector power pin description
|1||3.3V||all bank voltages fixed|
Table 14: FPGA SoC VCCO bank voltages
Absolute Maximum Ratings
VIN supply voltage (5.0V nominal)
|EP53A7HQI / EP53A7LQI datasheet|
|I/O Input voltage for FPGA I/O bank||-0.5||4.2||V||Intel Cyclone 10 LP datasheet|
|LED R6C-AL1M2VY/3T datasheet|
Table 15: Absolute maximum ratings
Recommended Operating Conditions
|VIN supply voltage (5.0V nominal)||4.75||5.25||V||same as USB-VBUS specification|
|I/O Input voltage for FPGA I/O bank||–0.5||3.6||V||Intel Cyclone 10 LP datasheet|
|Operating temperature range||0||+70|
|Winbond datasheet W9864G6GT|
Table 16: Recommended operating conditions
Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.
Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.
PCB thickness: ca. 1.65mm
Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.
Hardware Revision History
First Production Release
Table 17: Module hardware revision history
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
Table 18: Document change history
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