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Version 1


Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2022.2
  • PetaLinux
  • SD
  • ETH (use EEPROM MAC)
  • USB
  • I2C
  • RTC
  • FSBL for EEPROM MAC and CPLD access / petalinux patch
  • Special FSBL for QSPI Programming

Revision History

DateVivadoProject BuiltAuthorsDescription
Waldemar Hanemann
  • bugfix -boot up on first power up only. qspi x4 - device tree node entry
Waldemar Hanemann
  • 2022.2 update
Manuela Strücker
  • bugfix "os" folder
  • updated Petalinux config
    • added QSPI Partition for bootscr file
Manuela Strücker
  • 2021.2 update
Manuela Strücker
  • new Assembly variants
Manuela Strücker
  • new Assembly variants
Manuela Strücker
  • boot.scr file updated for 256 MB QSPI flash size variants
Manuela Strücker
  • update board files
  • update boot.scr file
John Hartfiel
  • bugfix missing binaries+ boot.scr file(supports now QSPI and SD boot with image.ub on SD)
John Hartfiel
  • 2020.2 update
  • add boot.scr file
  • petalinux fsbl patch (beta-version)
John Hartfiel
  • script update
John Hartfiel
  • script update for linux user
John Hartfiel
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
John Hartfiel
  • 2019.2 update
  • Vitis support
John Hartfiel
  • update for -1CR version only (256MB DDR3)
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features

John Hartfiel
  • DDR setup bugfix for l1if only
John Hartfiel
  • 2018.2 update
  • Board Part Files rework
John Hartfiel
  • new assembly variant
John Hartfiel
  • add assembly variant
  • script update
John Hartfiel
  • no design changes
  • set EEPROM MAC with FSBL+u-boot
  • FSBL for QSPI Programming
John Hartfiel
  • remove duplicated content
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
QSPI FlashProgramming QSPI fails with Vivado 2021.2use Vivado 2020.2 or 2019.2 for programming

Linux binaries are missing
boot.scr are only prepared for SD Boot
create and modify by yourself or use 2019.2 designsolved with 2020-04-01 update
Variant with 256MB DDR only(TE0720-03-1CR)wrong netboot offsetrecreate u-boot on petalinux with reduced netboot offset onlysolved with 2019-03-04 update
Known Issues




needed, Vivado is included into Vitis installation



Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0720-03-2IFC32if_1gbREV03|REV021GB32MB4GB2.5 mm connectorslow profile
TE0720-03-L1IFl1if_512mbREV03|REV02512MB32MB4GBNALP DDR3
TE0720-03-1QFL1qf_1gbREV03|REV021GB32MB4GB2.5 mm connectorslow profile
TE0720-03-61Q33FL1qf_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-61Q86KL1qf_1gbREV031GB32MB8GBNAAutomotive DDR and QSPI
TE0720-03-62I320M2if_1gbREV031GB32MBNANACAO: no Eth USB RTC VBAT CryptoKey
TE0720-03-62I330M2if_1gbREV031GB32MBNANACAO: no Eth USB RTC VBAT CryptoKey
TE0720-03-62I33FL2if_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-64I63FAl1if_512mbREV03512MB32MB8GBNALP DDR3
TE0720-03-1QFY1qf_1gbREV031GB32MB4GBNAno RTC
TE0720-03-61Q33MAY1qf_1gbREV031GB32MB8GBNAno RTC
TE0720-03-61Q33ML1qf_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-61Q42GAY1qf_256mbREV03256MB32MB32GBNAno RTC
TE0720-03-61Q43MA1qf_256mbREV03256MB32MB8GBNAautomotive Zynq mit IME1G16D3EEBG-15:EI
TE0720-03-62I33MAN2if_1gbREV031GB32MB8GBNAindustrieller Temperaturbereich; coated
TE0720-03-62I33MAY2if_1gbREV031GB32MB8GBNAno RTC
TE0720-03-62I33ML2if_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-S006C11qf_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S007C11qf_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0112if_1gbREV031GB32MB8GBNAcustom variant, no ETH
TE0720-03-S0122if_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0142if_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0161cr_256mbREV03256MB32MBNANAcustom variant, no RTC
TE0720-03-S0172if_1gbREV031GB32MB8GBNAcustom variant, no RTC
TE0720-03-61C33MAY1cf_1gbREV031GB32MB8GBNAno RTC
TE0720-03-S0131cf_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0202if_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S009C11qf_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S008C11qf_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0101qf_1gbREV031GB32MB8GBNAcustom variant
TE0720-04-61Q86PL1qf_1gbREV041GB32MB8GBNAAutomotive DDR and QSPI
TE0720-04-62I33ML2if_1gbREV041GB32MB8GB2.5 mm connectorslow profile
TE0720-04-64I63MAl1if_512mbREV04512MB32MB8GBNALP DDR3
TE0720-04-61Q43MA1qf_256mbREV04256MB32MB8GBNAautomotive Zynq and DDR
TE0720-04-61Q33ML1qf_1gbREV041GB32MB8GB2.5 mm connectorslow profile
TE0720-03-S0322if_1gbREV031GB32MB8GBNAcustom variant
TE0720-04-S001C11qf_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S007C11qf_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0162if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0191cf_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0222if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0232if_1gbREV031GB32MB8GBNAcustom variant
TE0720-04-S0252if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0262ef_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0272if_1gbREV041GB32MB8GB2.5 mm connectorscustom variant and low profile
TE0720-04-S0282if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0292if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0302if_1gbREV041GB32MB32GBNAcustom variant
TE0720-04-S0312if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0321qf_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0332if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0342if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0351cf_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0362if_1gbREV041GB32MB8GBNAcustom variant
TE0720-04-S0372if_1gbREV041GB32MB8GBNAcustom variant

*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • Used as reference carrier.
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
Additional Hardware


For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes<project folder>\misc\sd\Additional Initialization Script for Linux
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/ and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

  8. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0720 (optional)

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.src and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.


Not used on this Example.


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. Power On PCB

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    (can be skipped with config auto login in petalinux)
    petalinux login: root
    Password: root

    Note: Wait until Linux boot finished

  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C 0 Bus)
    i2cdetect -y -r 1	(check I2C 1 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
  4. Option Features
    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • scripts
      • add script on SD, content will be load automatically on startup (template is included in "<project folder>\misc\SD") 

Vivado HW Manager 

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
  • Monitoring: PHY LED

System Design - Vivado

Block Design

Block Design

PS Interfaces

Activated interfaces:

PS Interfaces


Basic module constraints

# Common BITGEN related settings for TE0720 SoM
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constraints

# Constraints for System controller support logic
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]

# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16]

Software Design - Vitis

For Vitis project creation, follow instructions from:



Template location: "<project folder>\sw_lib\sw_apps\"


TE modified 2022.2 FSBL


  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY
    • USB PHY Reset
    • Configure LED usage


TE modified 2021.2 FSBL


  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


Hello World App in Endless loop.


U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description






Note: for variants with 256MB DDR only, change NET Boot Address to 0x8000000 on boot.src file


Start with petalinux-config -c u-boot


  • CONFIG_ENV_OVERWRITE=y                       (used to overwrite default mac address and use from EEPROM)
  • CONFIG_ENV_IS_IN_FAT=y                            (needed to boot from SD card)
  • CONFIG_ENV_IS_IN_SPI_FLASH=y                  (needed to boot from QSPI flash)
  • # CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x1920000   (Calculate the start address of partition 3 "bootscr" in the QSPI flash. To do this, add the sizes of partitions 0, 1 and 2 together)
  • CONFIG_PREBOOT=echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo;

FSBL patch

Must be add manually, see template


Start with petalinux-config -c kernel




Start with petalinux-config -c rootfs


  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y                           (for web server app)
  • CONFIG_packagegroup-petalinux-utils=y      (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
  • CONFIG_util-linux-umount=y
  • CONFIG_util-linux-mount=y
  • CONFIG_ethtool=y                                      (for usage of phytool)
  • CONFIG_auto-login=y 

Add in <project folder>\os\petalinux\project-spec\meta-user\conf\petalinuxbsp.conf:

IMAGE_INSTALL:append += "\
phytool \

Device Tree

Device Tree (system-user.dtsi in device-tree and uboot-device-tree)
/include/ "system-conf.dtsi"
/ {

/* bugfix */
/* Uncomment on usage with single core variant only */
&amba {
	ptm@f889d000 {
		cpu = <&cpu0>;
*/    /* default */
/*------------------ QSPI PHY --------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

/*-------------------- ETH PHY ----------------*/
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;

/*-------------------- USB PHY ----------------*/  
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {
    iexp@20 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x20>;
    iexp@21 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x21>;
    /* Commend out if no RTC is fitted */
    rtc@6F {        // Real Time Clock
        compatible = "isl12022";
        reg = <0x6F>;


See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"


Script App to load from SD Card if available.


Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

  • bugfix -boot up on first power up only. qspi x4 - device tree node entry



Waldemar Hanemann

  • 2022.2 release


Thomas Dück

  • bugfix os folder
  • bugfix table of content
2022-01-25v.50Manuela Strücker
  • 2021.2 release
2021-12-16v.49Manuela Strücker
  • new assembly variants
2021-11-29v.46John Hartfiel
  • new assembly variants
2021-07-19v.45Manuela Strücker
  • boot.scr file updated for 256 MB QSPI flash size variants
2021-05-25v.44Manuela Strücker
  • update board files
  • update boot.scr file



John Hartfiel

  • Design update
2021-02-26v.41John Hartfiel
  • add issue notes
2021-02-17v.40John Hartfiel
  • 2020.2 release
2020-03-25v.39John Hartfiel
  • script update
2020-01-22v.38John Hartfiel
  • script update for linux user
2020-01-14v.37John Hartfiel
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
2019-12-19v.36John Hartfiel
  • 2019.2 release
2019-12-03v.34John Hartfiel
  • bugfix document link
2019-10-28v.33John Hartfiel
  • removed remove instructions that are no longer used


v.31John Hartfiel
  • Some FSBL notes
  • wrong link
2019-03-06v.28John Hartfiel
  • Fixed prebuilt issue for TE0720-03-1CR
2019-03-01v.27John Hartfiel
  • Known issue for TE0720-03-1CR linux design


v.26John Hartfiel
  • 2018.3 release finished (include design reworks)
2018-08-30v.25John Hartfiel
  • update documentation PS configuration



John Hartfiel
  • update l1if board parts


v.23John Hartfiel
  • 2018.4 release


v.22John Hartfiel
  • add assembly variant
2018-02-20v.20John Hartfiel
  • small documentation update
2018-01-09v.16John Hartfiel
  • Release 2017.4
  • Documentation update
2017-11-27v.14John Hartfiel
  • Typo correction
  • Design Files update
2017-11-22v.12John Hartfiel
  • Update HW list


John Hartfiel
  • Release 2017.2
  • Initial release
Document change history.

Legal Notices

Data Privacy

Please also note our data protection declaration at

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.



Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).


Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.


Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

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