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The Trenz Electronic TEI0015 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10.  Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

    • Speed Grade: C8 (Slowest)

    • Temperature: 0°C to 85°C

    • Package compatible device 10M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to 32 Mbyte (8Mbyte default)

  • USB 2.0 Multipurpose UART/FIFO IC (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)
  • SPI Flash - NOT INSTALLED (only special option)

  • 8x User LED 
  • 18 Bit 2MSPS Analog to Digital Converter
  • 2x SMA Female Connector

  • I/O interface: 23x GPIO - Arduino MKR compatible

  • Power Supply: 5V

  • Dimension: 86.5mm x 25mm

  • Others:

    • Instrumentation Amplifier

    • Differential Amplifier

    • Operational Amplifier

Block Diagram

TEI0015 block diagram

Main Components

TEI0015 main components
  1. SMA Connector, J5...6

  2. Amplifier, U12 - U14 - U6

  3. Voltage Reference, U8

  4. Analog to Digital Converter, U15

  5. Voltage Regulator, U10 - U13 - U16

  6. Switching Voltage Regulator/LDO, U11 - U4

  7. SDRAM Memory, U2

  8. Intel® MAX 10 FPGA, U1
  9. SPI Flash Memory, U5

  10. 12.00 MHz MEMS oscillator, U7

  11. FTDI USB2 to JTAG/UART adapter, U3

  12. User LEDs, D2...9

  13. FTDI configuration EEPROM, U9

  14. Configuration/Status LED (Red) , D10

  15. Power-on LED (Green), D1

  16. Push button, S1...2

  17. Micro USB Connector, J9

  18. 1x14 pin header, J2 (Not assembled)

  19. 1x6 pin header, J4 (Not assembled)

  20. 1x4 Header, J3 (Not assembled)

  21. 1x14 pin header, J1 (Not assembled)

Initial Delivery State

Storage device name



Quad SPI Flash


Not populated



FTDI configuration

Initial delivery state of programmable devices on the module

Configuration Signals

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

FPGA Reconfigration can be triggered by pressing push button S1.


Push ButtonPin HeaderNote


S1J2Connected to nCONFIG
Reset process.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
Bank 8J213.3VRESET
General I/Os to Pin Headers and connectors information

FPGA I/O Banks

FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2

41x14 Pin header, J1D2...5
112MHz Oscillator, U7CLK12M
2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 59

1x14 Pin header, J2

21x14 Pin header, J1DIO0...1
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
Bank 8

8User Red LEDs, D2...9LED0...7
1Push Button, S2USER_BTN
FPGA I/O Banks

Micro-USB Connector

The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.

PinsConnected toNote

FTDI FT2232H U3, DP pin


FTDI FT2232H U3, DM pin

Micro USB-2 connector pins

JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

JTAG Signal

Pin Header Connector



JTAG_ENJ4-2Pulled-up to 3.3V
JTAG pins connection

On-board Peripherals

SPI FlashU5
OscillatorU712 MHz clock source
ADCU12, U14Analog to Digital Converter
Push ButtonsS1...2
8x User LEDsD2...9Red LEDs
On board peripherals


TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

Data input/output

DQ0 ... DQ15

bank 6

Data mask

DQM0 ... DQM1

bank 6

ClockCLKbank 3-
Control Signals


bank 3

Chip select


bank 3

Clock enable


bank 3

Row Address Strobe


bank 3

Column Address Strobe

WEbank 3Write Enable
SDRAM interface IOs and pins


The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4User configurable
BDBUS1BDBUS1FPGA bank 8, pin B4User configurable
BDBUS2BDBUS2FPGA bank 8, pin B5User configurable
BDBUS3BDBUS3FPGA bank 8, pin A6User configurable
BDBUS4BDBUS4FPGA bank 8, pin B6User configurable
BDBUS5BDBUS5FPGA bank 8, pin A7User configurable
BDBUS6BDBUS6FPGA bank 6, pin C11
BDBUS7BDBUS7FPGA bank 3, pin J7
BCBUS0BCBUS0FPGA bank 5, pin J9
BCBUS1BCBUS1FPGA bank 3, pin K5
BCBUS2BCBUS2FPGA bank 3, pin L4
BCBUS3BCBUS3FPGA bank 3, pin L5
BCBUS4BCBUS4FPGA bank 3, pin N12
FTDI chip interfaces and pins

SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

Signal Schematic NameConnected toNotes
F_CSFPGA bank 8, pin B3Chip select
F_CLKFPGA bank 8, pin A3Clock
F_DIFPGA bank 8, pin A2Data in / out

FPGA bank 8, pin C4

Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2Data in / out
Quad SPI Flash memory interface


The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

SchematicConnected toNotes


I2C EEPROM interface MIOs and pins


The TEI0015 board is equipped with the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC.

PinsConnected toNotes


Diff Amplifier U14, VOUT-
IN-Diff Amplifier U14, VOUT+
SDIFPGA, bank 2, pin M2, ADC_SDI
SDOFPGA, bank 2, pin M1,  ADC_SDO
SCKFPGA, bank 2, pin N3,  ADC_SCK
CNVFPGA, bank 2, pin N2, ADC_CNV
A2D converter interface and pins


DesignatorColorConnected toActive LevelNote
D2...9RedLED1...8Active HighUser LEDs
D10RedCONF_DONEActive LowConfiguration DONE LED
D1Green3.3V Active HighAfter power on it will be on.
On-board LEDs

Push Bottuns

DesignatorConnected toFunctionalityNote
S1RESETGeneral reset
S2USER_BTNUser push buttonConnected to FPGA Bank 8.
On-board Push Buttons

Clock Sources

Clock SourceSchematic NameFrequencyNote
MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA SoC bank 2, pin H6.


Power and Power-On Sequence

Power Supply

The module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

FPGATypical Current
Intel MAX 10 10M08 FPGATBD*
Power Consumption

* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

Power Distribution

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.

Power Rails

Power Rail Name


J2 Pin


J9 Pin

VINJ2-13-Input5 V - Pin Header


-J9-1Input5 V - USB Connector
Module power rails.

Bank Voltages


Schematic Name


Bank 1AVCCIO1A3.3V
Bank 1B


Bank 2VCCIO23.3V
Bank 3VCCIO33.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V

Bank 8VCCIO83.3V

Intel MAX 10 SoC bank voltages.

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnitReference Document


Supply voltage4.755.25V
CH1-, CH1+Analog input voltage on amplifier U12 pin 1, 10-3030VAD8251 datasheet


Storage Temperature-25+85°C
Absolute maximum ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)-1010VAD8251 datasheet


0+70°CW9864G6JT-6 datasheet
Recommended operating conditions.

Physical Dimensions

Module size: 25 mm × 86.5 mm.  Please download the assembly diagram for exact numbers.

PCB thickness: 1.22 mm.

Physical Dimension

Currently Offered Variants 

Trenz shop TEI0015 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History

DateRevisionChangesDocumentation Link
Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Board hardware revision number.

Document Change History


  • multiple sections updated


  • Technical Specifications updated

  • Power Rails updated



  • --
Document change history.


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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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