Template Revision 2.6 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note:
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Table of contents |
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Refer to http://trenz.org/te0xyz-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Design supports following carriers:
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - Xilinx devices
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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Not used on this Example.
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
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Note:
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Activated interfaces:
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
set_property PACKAGE_PIN E3 [get_ports PWM_L] set_property PACKAGE_PIN F4 [get_ports PWM_R] set_property IOSTANDARD LVCMOS18 [get_ports PWM_*] #set_property PACKAGE_PIN T2 [ get_ports USER_BTN_DOWN ] #set_property PACKAGE_PIN U2 [ get_ports USER_BTN_UP ] #set_property PACKAGE_PIN U1 [ get_ports USER_BTN_RIGHT ] #set_property PACKAGE_PIN R1 [ get_ports USER_BTN_LEFT ] #set_property PACKAGE_PIN T1 [ get_ports USER_BTN_OK ] #set_property IOSTANDARD LVCMOS18 [ get_ports USER_BTN_* ] set_property PACKAGE_PIN P3 [get_ports {USER_SW[0]}] set_property PACKAGE_PIN P2 [get_ports {USER_SW[1]}] set_property PACKAGE_PIN M1 [get_ports {USER_SW[2]}] set_property PACKAGE_PIN L1 [get_ports {USER_SW[3]}] set_property PACKAGE_PIN K1 [get_ports {USER_SW[4]}] set_property PACKAGE_PIN J2 [get_ports {USER_SW[5]}] set_property PACKAGE_PIN M4 [get_ports {USER_SW[6]}] set_property PACKAGE_PIN M5 [get_ports {USER_SW[7]}] set_property IOSTANDARD LVCMOS18 [get_ports USER_SW*] set_property PACKAGE_PIN U2 [get_ports {USER_BTN_UP}] set_property PACKAGE_PIN U1 [get_ports {USER_BTN_RIGHT}] set_property PACKAGE_PIN T2 [get_ports {USER_BTN_DOWN}] set_property PACKAGE_PIN R1 [get_ports {USER_BTN_LEFT}] set_property PACKAGE_PIN T1 [get_ports {USER_BTN_OK}] set_property IOSTANDARD LVCMOS18 [get_ports USER_BTN*] set_property PACKAGE_PIN P1 [get_ports {LED[0]}] set_property PACKAGE_PIN N2 [get_ports {LED[1]}] set_property PACKAGE_PIN M2 [get_ports {LED[2]}] set_property PACKAGE_PIN L2 [get_ports {LED[3]}] set_property PACKAGE_PIN J1 [get_ports {LED[4]}] set_property PACKAGE_PIN H2 [get_ports {LED[5]}] set_property PACKAGE_PIN L4 [get_ports {LED[6]}] set_property PACKAGE_PIN L3 [get_ports {LED[7]}] set_property IOSTANDARD LVCMOS18 [get_ports LED*] set_property PACKAGE_PIN F2 [get_ports {VGA_R[0]}] set_property PACKAGE_PIN F1 [get_ports {VGA_R[1]}] set_property PACKAGE_PIN G2 [get_ports {VGA_R[2]}] set_property PACKAGE_PIN G1 [get_ports {VGA_R[3]}] set_property PACKAGE_PIN C2 [get_ports {VGA_G[0]}] set_property PACKAGE_PIN D2 [get_ports {VGA_G[1]}] set_property PACKAGE_PIN D1 [get_ports {VGA_G[2]}] set_property PACKAGE_PIN E1 [get_ports {VGA_G[3]}] set_property PACKAGE_PIN A3 [get_ports {VGA_B[0]}] set_property PACKAGE_PIN A2 [get_ports {VGA_B[1]}] set_property PACKAGE_PIN B2 [get_ports {VGA_B[2]}] set_property PACKAGE_PIN B1 [get_ports {VGA_B[3]}] set_property PACKAGE_PIN B7 [get_ports {VGA_VS[0]}] set_property PACKAGE_PIN A6 [get_ports {VGA_HS[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {VGA_HS[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {VGA_VS[0]}] set_property PACKAGE_PIN J3 [get_ports CLK_25MHZ] set_property IOSTANDARD LVCMOS18 [get_ports CLK_25MHZ] # SEG_C[0] = SEG_CA set_property PACKAGE_PIN E4 [get_ports {SEG_C[0]}] set_property PACKAGE_PIN D3 [get_ports {SEG_C[1]}] set_property PACKAGE_PIN N5 [get_ports {SEG_C[2]}] set_property PACKAGE_PIN P5 [get_ports {SEG_C[3]}] set_property PACKAGE_PIN N4 [get_ports {SEG_C[4]}] set_property PACKAGE_PIN C3 [get_ports {SEG_C[5]}] set_property PACKAGE_PIN N3 [get_ports {SEG_C[7]}] set_property PACKAGE_PIN R5 [get_ports {SEG_C[6]}] set_property IOSTANDARD LVCMOS18 [get_ports SEG_C*] set_property PACKAGE_PIN A8 [get_ports {SEG_AN[0]}] set_property PACKAGE_PIN A9 [get_ports {SEG_AN[1]}] set_property PACKAGE_PIN B9 [get_ports {SEG_AN[2]}] set_property PACKAGE_PIN A7 [get_ports {SEG_AN[3]}] set_property PACKAGE_PIN B6 [get_ports {SEG_AN[4]}] set_property IOSTANDARD LVCMOS33 [get_ports SEG_AN*] |
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For SDK project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2018.3 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2018.3 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2018.3 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2018.3 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2018.3 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
TE modified 2018.3 FSBL
General:
Module Specific:
TE modified 2018.3 FSBL
General:
Xilinx default PMU firmware.
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH is not set
Change platform-top.h:
#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO_MMC \ "dfu_mmc_info=" \ "set dfu_alt_info " \ "${kernel_image} fat 0 1\\\\;" \ "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" /*Required for uartless designs */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #ifdef CONFIG_DEBUG_UART #undef CONFIG_DEBUG_UART #endif #endif /*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */ #define CONFIG_ZYNQMP_EEPROM #ifdef CONFIG_ZYNQMP_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_CMD_EEPROM #define CONFIG_ZYNQ_EEPROM_BUS 1 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA #endif |
/include/ "system-conf.dtsi" / { }; #include <dt-bindings/gpio/gpio.h> /* SD */ &sdhci0 { disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; //snps,usb3_lpm_capable; //snps,dis_u3_susphy_quirk; //snps,dis_u2_susphy_quirk; //phy-names = "usb2-phy","usb3-phy"; //phys = <&lane1 4 0 2 26000000>; //maximum-speed = "super-speed"; }; / { leds { compatible = "gpio-leds"; ndp_en { label = "ndp_en"; gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; default-state = "on"; }; ssd_sleep { label = "ssd_sleep"; gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; default-state = "on"; }; usb_reset { label = "usb_reset"; gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; |
Start with petalinux-config -c kernel
Changes:
CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
Start with petalinux-config -c rootfs
Changes:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Webserver application accemble for Zynq access. Need busybox-httpd
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No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
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