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Overview

Firmware for TEI0022 Intel MAX 10 with designator U41: 10M08SAU169C8G

Feature Summary

• Fan control
• JTAG control
• LED control
• UART
• User button
• Power management
  • Power regulator mode control
  • FMC Power control
• Reset management
• Configuration sheme control

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

DCDC Mode Control

The mode signals are connected to "1".

Fan Control

Can be enabled/disabled through the Intel Cyclone V HPS "CPU_GPIO4".

FMC Voltage Control

The power is enabled if signal "CPU_GPIO3" is set to "1" and there is an FMC card. Then, the +12.0 V level is enabled. After that, the adjustable voltage is enabled. Finally, the +3.3 V level is enabled. Then, the signal "FMC_PG_C2M" is asserted.

JTAG Control

The FTDI JTAG is connected to the Intel MAX10, the Intel Cyclone V HPS and Fabric and to the FMC Connector according to the following table.

LED Control

The leds signals their power good status.

UART

The second channel of the JTAG FTDI interface delievers an UART connection to the Intel Cyclone V fabric.

User Button

The User Button is connected to the FPGA.

Power Management

The power sequencing is handled inside the system controller according to the next figure.

The FMC power sequencing depends on the assertion through the signals "CPU_GPIO3" and "FMC_PRSNT_M2Cn". If both of them are asserted, the +12.0 V level starts, followed by the adjustabel voltage level with the according pre-driver voltage and finally, the +3.3 V level is started.

The FMC adjustable voltage selection can be done manually by the switches or automatically by the Intel Cyclone V HPS. The choice is done via the switches according to the next table. The voltage for the Intel Cyclone V HPS pre-driver is selected according to the voltage setting.

Reset Management

The reset buttons are connected via the system controller to the according reset locations. That means that, if the reset button S1 or the brown-out detection is asserted, the Cyclone V should be reseted. If the warm reset button S3 is asserted, the Cyclone V should be warm reseted. If the FPGA reset button S4 is asserted, the FPGA could be reseted.

Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV01 to REV02

• Changed pin connections
• Changed JTAG connection
• Changed reset connection
• Changed FMC Vadj Voltage selection
• Changed power sequencing

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices