Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TEB0707 is a carrier for 4 x 5 Trenz Electronic modules. It provides three high speed and one low speed CRUVI extension connectors. For more information, please refer to the CRUVI B2B Connectors. The TEB0707 is integrated with an Intel MAX10 FPGA as system controller and is equipped with a Micro USB2.0 Socket with FTDI to JTAG/UART solution, RJ45 LAN Socket, USB A Socket, Micro SD Card Socket, User LEDs, Push Buttons and DIP Switches for controlling the SoM.

Refer to http://trenz.org/teb0707-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension



Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






|


Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Barrel Jack Power Supply, J1
  2. Voltage Regulator, U1
  3. Micro SD Card Socket, J8
  4. Micro USB2.0 Socket, J15
  5. FT2232H FTDI, U8
  6. USB A Socket, J9
  7. RJ45 LAN Socket, J2
  8. SDIO Port Expander, U4
  9. Jumpers, J4...7
  10. Push Button (Reset), S2
  11. DIP Switch, S1
  12. B2B Connector, JB3
  13. B2B Connector, JB2
  14. B2B Connector, JB1
  15. Intel MAX 10 FPGA, U6
  16. High Speed CRUVI Connector, J10
  17. High Speed CRUVI Connector, J11
  18. High Speed CRUVI Connector, J12
  19. Low Speed CRUVI Connector, J13
  20. User Push Button, S3
  21. Pin header, J3

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

EEPROMProgrammed

FTDI Configuration


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.


MODE Signal State

Boot Mode

MODE

Boot Mode:

  • SD Card (Low)
  • QSPI (High)
PROGMODE

Programming Mode:

  • select between CPLD (low, closed, on)
  • on SoM or FPGA/SoC (high, open, off )



Signal

Connected toI/ONote

Reset

Push Button, S2OutModule Reset signal


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B)

Interfaces and Number of I/O signals connected to the B2B connectors for Trenz 4x5 modules:

B2B ConnectorInterfaceI/O Signal CountConnected toNotes
JB1


Ethernet LAN4x Diff pairsRJ45 Socket, J2
SD  Card6 x Single EndedIO Expander, U4
I/Os20x Single EndedMAX10 FPGA Bank 6, U6
CRUVI

12x Diff pairs/24x Single ended

4x Single Ended

High Speed CRUVI, J12CRUVI C
SoM Control Signals5x Single EndedMAX10 FPGA, U6
I/Os8x Single endedMAX10 FPGA Bank 8, U6
JB2

CRUVI

12x Diff pairs/24x Single ended

4x Single Ended

High Speed CRUVI, J10CRUVI A
CRUVI6x Diff pairs/12x Single endedHigh Speed CRUVI, J11CRUVI B
JTAG4x Single EndedFPGA Bank 5, U6
JB3CRUVI

6x Diff pairs/12x Single ended

4x Single Ended

High Speed CRUVI, J11CRUVI B
USB 

1x Diff pair,

2x Single Ended

USB A, J9


CRUVI B2B Connectors

The TEMB0707 is equipped with a Low Speed Connectors J 13 and three High Speed Connector J10...12. These connectors are provided for CRUVI extension cards. More information is provided in the  B2B Connectors section.

SpeedDesignatorsSchematicConnected toNotes
High



CRUVI C, J12A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1
MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCKMAX10 FPGA Bank 8, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HI, HO, RESET B2B, JB1
High


CRUVI B, J11A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1
MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCKMAX10 FPGA Bank 2/3, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HSI, HSO, RESET B2B, JB3
High



CRUVI A, J13



A0...A5 (N/P)B2B, JB2
B0...B5 (N/P)B2B, JB2

MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCK

MAX10 FPGA Bank 2/3, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HSI, HSO, RESET B2B, JB2
LowCRUVIX0...X7MAX10 FPGA Bank 1A, U6



JTAG Interface

JTAG signals form FTDI U8  are routed to MAX10 CPLD. Via dip setting JTAG of MAX10 or JTAG of the connected Trenz 4x5 module can be selected. Forwarding signals to SoM is MAX10 Firmware dependent.

JTAG Signal

MAX10 Pin Bank 1B, U6

Connected to

TMSG1FTDI (U8) - ADBUS3
TDIF5FTDI (U8) - ADBUS1
TDOF6FTDI (U8) - ADBUS2
TCKG2

FTDI (U8) - ADBUS0

JTAGENE5Dip S1-4


JTAG access to the Trenz 4x5 module is through B2B connector JB2.

JTAG Signal

MAX10 Pin Bank5, U6

B2B Connector

M_TMSL12JB2-94
M_TDIL13JB2-96
M_TDOJ10JB2-100
M_TCKH8

JB2-98

VCCJTAGJ11, J12JB2-92


SD Card socket

The TEB0707 is equipped with an Micro SD Card slot, J8. For levelshifting an IO Expander (U4) is used.

Pin SchematicConnected toNotes
DAT0...3ESD_DAT0...3B2B, JB1Through IO Expander, U4
CMDESD_CMDB2B, JB1Through IO Expander, U4
VDD3.3V_SDB2B, JB1Through IO Expander, U4
CLKESD_CLKB2B, JB1Through IO Expander, U4
DLTSD_CDFPGA Bank 3, U6Card detect.


Micro USB2.0 Socket

There is a micro USB2.0 Socket, J15 provided in order to communicate with the FTDI, U8.

Pin SchematicConnected toNotes
D+O2-D_PB2B, JB3Through Line Filter, L4
D-O2-D_NB2B, JB3Through Line Filter, L4
VbusVBUSB2B, JB3


 USB A Socket

The SoM USB 2.0 signals are routed to a USB A socket (host).

Pin SchematicConnected toNotes
Data+O2-D_PB2B, JB3Through Line Filter, L1
Data-O2-D_NB2B, JB3Through Line Filter, L1
VCCUSB_VBUSB2B, JB3


RJ45 LAN Socket

There is a RJ45 Ethernet LAN MagJack, J2 connected to B2B, JB1.

Pin SchematicConnected toNotes
2PHY_MDI0_PB2B, JB1
3PHY_MDI0_NB2B, JB1
4PHY_MDI1_PB2B, JB1
5PHY_MDI1_NB2B, JB1
6PHY_MDI2_PB2B, JB1
7PHY_MDI2_NB2B, JB1
8PHY_MDI3_PB2B, JB1
9PHY_MDI3_NB2B, JB1
VCCETH-VCCB2B, JB1
Green LEDETH1_LED0Intel MAX 10, U6MAX10 Firmware dependent
Yellow LEDETH1_LED1Intel MAX 10, U6MAX10 Firmware dependent


Jumpers

There are three Jumpers provided to choose the CRUVI Extension power voltage.

DesignatorSchematicConnected toNotes
J14VCCIO_CCB2B, JB2CRUVI C
J16VCCIO_CBB2B, JB2CRUVI B
J17VCCIO_CAB2B, JB2CRUVI A


Pin Header

DesignatorSchematicConnected toNotes
J3VBATB2B, JB1


Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Test PointSignalConnected toNotes
TP13.3VRegulator, U1
TP2VINVoltage Protection, U2
TP4IOVRegulator, U3
TP53.3VPower Switch, Q1
TP6C5VINPower Switch, Q2


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
Intel MAX 10U6
FTDIU8
TEB0707 TRM#EEPROMU10FTDI, programmed with Xilinx licence
OscillatorU7
TEB0707 TRM#LEDsD1...8
DIP SwitchS1
Push ButtonsS2, S3


Intel Max10 CPLD

The TEB0707 is quipped with an Intel Max10 as CPLD used for levelshifting of 3.3V signals on CRUVI connectors, JTAG/UART forward to modules, Module control pis, power sequencing and IO voltage selection along with providing User Push buttons, LEDs and switches. For complete information, please see the TEB0707 MAX10 CPLD.

FTDI FT2232H

The FTDI chip (U8) converts signals from USB2 to variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip which is used in  Multi-Protocol Synchronous Serial Engine (MPPSE) mode for JTAG. 

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U10.

PinSchematicConnected toNotes
ADBUS0TCKFPGA Bank 1B, U6JTAG interface
ADBUS1TDIFPGA Bank 1B, U6
ADBUS2TDOFPGA Bank 1B, U6
ADBUS3TMS

FPGA Bank 1B, U6

BDBUS0F_UART_TXFPGA Bank 1B, U6UART Transmitter output
BDBUS1F_UART_RXFPGA Bank 1B, U6UART Receiver Input
OSCIOSCIOscillator, U7Clock 12 MHz
EECSEECSEEPROM, U10EEPROM Contains FTDI configuration
EECLKEECLKEEPROM, U10
EEDATAEEDATAEEPROM, U10
DM/DPFD_N/ FD_PMicro USB, J15USB to UART
nRESET3.3V3.3V


LEDs

The functions of the LEDs are MAX10 Firmware dependent. See TEB0707 MAX10 CPLD LEDs.

DesignatorColorSchematicConnected toActive LevelNote
D1greenLED3FPGA Bank 8Active High
D2greenLED5FPGA Bank 8Active High
D3greenLED7FPGA Bank 8Active High
D4redLED4FPGA Bank 3Active High
D5redLED6FPGA Bank 2Active High
D6redLED8FPGA Bank 8Active High
D7redLED2FPGA Bank 3Active High
D8greenLED1FPGA Bank 3Active High


EEPROM

The EEPROM IC, U8 contains the FTDI configuration and is prprogrammed with Xilinx JTAG licence.

PinSchematicConnected toNotes
CSEECSFTDI, U8
CLKEECLKFTDI, U8
DINEEDATAFTDI, U8


DIP Switch

There is a DIP Switch provided for user controlling of settings. Dip1..3 are connected to MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 Dips.

PinSchematicFunction (in standard Firmware)Notes
DIP1DIP1Forwarded to IO so SoM

MAX10 firmware dependent.

DIP2DIP2IO Voltage selection1.8V ('high', open, OFF), 2.5V ('low', closed, ON)
DIP3DIP3 (PROGMODE)Programming mode (JTAG selection on Trenz 4x5 module)Select between FPGA/SoC (high, open, OFF ) or CPLD (low, closed, ON), MAX10 firmware dependent.
DIP4JTAGENJTAG SelectionJTAG mode between CPLD (high, closed, ON) or SoM (low, open, OFF)


Push Buttons

Buttons are connected MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 CPLD Buttons

DesignatorSchematicFunction (in standard Firmware)Notes
S2RESETSoM ResetHardware debounced.
S3BUTTON1User Buttondebounced in Max10 FPGA


Clock Sources

MEMS U7 Oscillator is nedded for FTDI. It is  additionally connectd to MAX 10 FPGA Bank 2 Pin H4 and can be used in custom Firmware.

DesignatorDescriptionFrequencyNote
U7MEMS Oscillator12 MHz


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • |Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence




Power Rails


Power Rail Name

B2B Connector

JB1 Pin

B2B Connector

JB2 Pin

B2B Connector

JB3 Pin

DirectionNotes
VCCIO_CA-8, 10-Output
VCCIO_CB-2, 4, 6-Output
VCCIO_CC10, 12--Output

3.3V 

14, 16--Output
M1.8VOUT40--Input
M3.3VOUT-9, 11-Input
ETH-VCC13--Input


Bank Voltages

Below MAX10 CPLD Bankvoltages are summarized.

Bank          

Schematic Name

Voltage

Notes
Bank 1A3.3V3.3V
Bank 1B

3.3V

3.3V
Bank 23.3V3.3V
Bank 33.3V3.3V
Bank 5VCCJTAG
from SoM
Bank 6VCCIO_CC

Variable

Bank 83.3V3.3V




Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

CRUVI Connectors

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
5VINInput supply Voltage-4060V
T_STGStorage Temperature-4085°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
Input supply Voltage4.065.58VSee the OV/UV in the carrier datasheets.
T_OPT070°CSee  Push Button datasheet.


Physical Dimensions

PCB thickness: 1.7 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TEB0707 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
2020-11-20REV02first production releaseREV02
2020-04-01REV01Prototypes-


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • Initial Reslease

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all

  • --


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