DIP Switch Configuration

Similar to the traditional configuration memories, SPI serial Flash memories must be loaded with the configuration data. SPI serial Flash memories have a single interface for programming, but there are multiple methods to deliver the data to this interface. This section discusses the hardware setup, the PROM file generation flow and the software flow for ISP (indirect in-system programming) of a Trenz Electronic TE0300 SPI serial Flash configuration PROM through the JTAG interface of a Xilinx Spartan-3E FPGA using Xilinx iMPACT 10.1 (with other version the procedure should be almost the same).

To write the SPI Flash memory, perform the following steps:

DIPswitch

on (left)

off (right)

S1

X

X

S2

Run

 

S3

-

PON

S4

X

X

TE0300 Example

The following example shows the case of iMPACT 10.1.

For further information about indirect (SPI over JTAG) in-system programming of SPI Flash memories, please see Xilinx Application Note XAPP974 "Indirect Programming of SPI Serial Flash PROMs with Spartan-3A FPGAs".

When downloading via parallel JTAG programmer to FPGA, it can happen that programming fails with Error: "'1' : Programming terminated. DONE did not go high." Try setting DIP switch S4 to JTAG-only. A bug in certain Xilinx iMPACT versions can cause this.