This section describes how to configure the TE USB FX2 module and access some of its resources.
To program the firmware in the EEPROM, the IIC bus should be correctly configured.
To program the bitstream in the Flash, the SPI bus should be correctly configured.
TE USB FX2 modules can be configured through a host computer with the following system requirements:
- Operating system: Microsoft Windows 2000, Microsoft Windows XP, Microsoft Vista, Microsoft Windows 7 or above;
- Xilinx ISE 10.1 or later for indirect SPI in-system programming (ISP) (for Spartan-3E aka TE0300, see Xilinx Answer AR #25377);
- Xilinx EDK for some reference designs;
- Interface: USB host;
- JTAG cable with flying leads.
- SPI USB cable with flying leads (for TE0300): direct SPI in-system programming (ISP) is only possible until iMPACT 11.x.
The JTAG interface allows a fast, frequent but volatile configuration (only the FPGA is programmed and not the SPI Flash) of the TE USB FX2 module. However, only through the JTAG interface it is possible to develop and debug with Xilinx tools (e.g. Xilinx ChipScope, Xilinx Microprocessor Debugger. The JTAG interface allows also a occasional, non-volatile on-site operations such as SPI Flash bitstream download.
Configuration of the TE USB FX2 module through a USB host is recommended for occasional, non-volatile on-site operations such as firmware upgrade or SPI Flash bitstream download.
TE USB FX2 module is equipped with a Cypress EZ-USB FX2 controller to provide a high-speed USB 2.0 interface. The controller uses 4 interfaces (see here):
- USB interface (to USB connector): connection with the host computer;
- I2C interface (to EEPROM): the I2C interface connects the USB controller to the EEPROM chip, which stores vendor ID and device ID. See chapter DIP Switch for available options.
- SPI interface (to FPGA and Flash): the SPI interface id used to communicate with the FPGA and to access the SPI serial Flash chip. The SPI interface allows a fast, frequent and non-volatile configuration of the TE0300 module (through J3) and TE0320 module (through B2B connection).
- FIFO interface (to FPGA): the FIFO interface provides a high-speed communication channel with the FPGA. The interface can transfer up to 48 MB/s burst rate.