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Overview

Firmware for RFSoC module CPLD with designator U31: LCMX02-640HC

Feature Summary

• Firmware
• Power Management
• JTAG routing
• Boot Mode
• User IO
• LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.

Power

In this module the CPLD is responsible for controlling the power of the module. There are different power regulators or DC/DC converters whose outputs can be controlled by an enable signal. At the same time the outputs can also be monitored by power-good signals.

Power-on Sequencing

According to the Xilinx instructions the power regulator or DC-DC converter must be switched on or off in a certain order. This is called power-on or power-off sequencing.To implement power-on sequencing correctly, a state machine must be running there. In the following you can see the State Machine Diagram.

• pg_all <= PG_PS_PL & PG_GR1 & PG_GR2 & PG_VCCRF & PG_RF_ADC & PG_RF_DAC
• If por is high then POR_B (power-on reset signal) will be deactivated.

LED

• The period for erery blink (*o) is 0.5sec.

User IO

• FPGA_IO1 (AE16 of RFSoC) is connected with CPLD_IO2 (S1-3 Dip switch on the carrier board) when the FPGA is programmed correctly otherweise this pin is high impedance. After configuration of the FPGA can user use this pin as input.
• FPGA_IO0 (AE18 of RFSOC) is connected with LED on the RFSoC module  (D1) if the FPGA is programmed completely otherweise this LED (D1) blinks according to the state of the power-on sequencing. After configuration of the FPGA can be controlled this LED (D1) by user.

If the FPGA correctly programmed (DONE signal is high) and  the power-on sequencing state is RDY then the User IOs can be shown in the following table:

Boot Mode

Boot Modes can be selected via B2B Pin Mode.

Appx. A: Change History and Legal Notices

Revision Changes

• REV00 to REV01
  • transfer verilog to vhdl
  • power stagemachine, add power down cyclus on error state
  • bugfix: Power Good(CPLD_IO3) depends now on module power sequencing
  • LED status changed
  • LED controllable by USR after power up
  • CPLD_IO2 connected to FPGA IO (can be controlled by user)
  • constrains and buffer changes for JTAG

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices