Template Revision 2.6
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Important General Note:
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Note for Download Link of the Scroll ignore macro:
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Table of Contents |
The Trenz Electronic TEI0015 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.
Notes :
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Intel® MAX 10 Commercial [10M08SAU169C8G]
Package: UBGA-169
Speed Grade: C8 (Slowest)
Temperature: 0°C to 85°C
Package compatible device 10M02...10M16 as assembly variant on request possible
SDRAM Memory up to 64Mb, 166MHz
Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
18 Bit 2MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO
Power Supply:
5V
Dimension: 86.5mm x 25mm
Others:
Instrumentation Amplifier
Differential Amplifier
Operational Amplifier
add drawIO object here.
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Notes :
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SMA Connector, J5...6
Amplifier, U12 - U14 - U6
Series Voltage Reference, U8
Analog to Digital Converter, U15
Voltage Regulator, U10 - U13 - U16
Switching Voltage Regulator, U11 - U4
SDRAM Memory, U2
SPI Flash Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
FTDI configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB Connector, J9
1x14 pin header, J2 (Not assembled)
1x6 pin header, J4 (Not assembled)
1x4 Header, J3 (Not assembled)
1x14 pin header, J1 (Not assembled)
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
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Notes :
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example:
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The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
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JTAG access to the TEI0015 SoM through pin header connector J4.
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Notes :
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
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The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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The TEI0015 board is equipped with the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC.
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
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To power-up the module, power supply with minimum current capability of 1A is recommended.
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* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.
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Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.22 mm.
In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
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Set correct link to the shop page overview table of the product on English and German. Example for TE0728: ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ if not available, set. |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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