Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Note for Download Link of the Scroll ignore macro: |
Table of Contents |
Overview
The Trenz Electronic TEM0005-02 is a low-cost, small FPGA module with Microsemi SmartFusion2 FPGA SoC and 32 MByte flash memory for configuration and operation. SmartFusion2 combines a 166 MHz Cortex-M3 MCU with 256 KByte Flash and 80 KByte SRAM as well as 12 kLUT FPGA Core Logic.
Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC/FPGA
- Package: VFG400
- Device: M2S005, M2S010, M2S025,M2S050,M2S060*
- Engine: VFG
- Speed: -1, Standard*, **
- Temperature: C, I,*, **
- RAM/Storage
- Low Power DDR3
- Data width: 8/16bit
- Size: def. 2Gb*
- Speed: 20ns***
- QSPI
- Data width: 8 bit
- size: 256 M bit *
- 2Kb EEPROM
- On Board
- Crypto Authentication IC
- Voltage monitor IC
- 10/100 Mbps PHY Ethernet
- Interface
- Power
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used FPGA and DDR3 combination
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Microsemi SmartFusion, U2
- Reg, U7
- EEPROM, U4
- 10/100 Mb Ethernet, U1
- QSPI Flash, U3
- Authentication IC, U6
- DDR3 Memory, U5
- B2B Connector, J1
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| EEPROM | Not Programmed |
| DDR3 SDRAM | Not Programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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Signal | B2B | I/O | Note |
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RESET
| J1-11 |
| Active low reset |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG Interface
JTAG access to the TEM0005 SoM through B2B connector J1.
JTAG Signal | B2B Connector |
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TMS | J1-14 | TDI | J1-8 | TDO | J1-10 | TCK | J1-12 | JTAG_EN | J1-7 |
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Test Points
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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Test Point | Signal | Connected to | Notes |
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TP1 | CLKOUT | Regulator, U7 |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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QSPI | U3 |
| DDR3 SDRAM | U5 |
| EEPROM | U4 |
| Authentication IC | U6 |
| Ethernet | U1 |
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Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
MIO Pin | Schematic | U?? Pin | Notes |
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EEPROM
MIO Pin | Schematic | U?? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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Clock Sources
Designator | Description | Frequency | Note |
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Y3 | Crystal Oscillator | 25 MHz |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 1.5 A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Voltage Monitor Circuit
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
Power Rail Name | B2B Connector JM1 Pin | Direction | Notes |
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3.3V | 1, 2, 3, 4 | Output |
| VDDI6 | 22 | Input |
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Bank Voltages
| Schematic Name | | Notes |
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Bank0 | VDDI0 | 1.5V |
| Bank1 | VDDI1 | 3.3V |
| Bank2 | VDDI2 | 3.3V |
| Bank3 | VDDI3 | 3.3V |
| Bank4 | VDDI4 | 3.3V |
| Bank5 | VDDI6 | ? |
| Bank6 | VDDI6 | ? |
| Bank7 | VDDI7 | 3.3V |
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Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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VIN | Input Supply Voltage |
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| V | STG_T | Storage Temperature |
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| °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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VIN |
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| V | See ???? datasheets. | OPT_T |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: 1.6 mm.
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Date | Revision | Contributor | Description |
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| | | | -- | all | | |
|
Disclaimer
Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
----------------------------------------------------------------------- |
Note for Download Link of the Scroll ignore macro: |
Table of Contents |
Overview
The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...
Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- <Replace for module use "SoC/FPGA" for Carrier "Modules">
- RAM/Storage
- On Board
- Interface
- Power
- Dimension
- Notes
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
|
- ...
- ...
- ...
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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Quad SPI Flash |
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| EEPROM |
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| System Controller CPLD |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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MODE Signal State | Boot Mode |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
|
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
JTAG Signal | B2B Connector |
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TMS |
| TDI |
| TDO |
| TCK |
| JTAG_EN |
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MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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MIO Pin | Connected to | B2B | Notes |
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Test Points
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
---|
10 | PWR_PL_OK | J2-120 |
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Test Point | Signal | Connected to | Notes |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
MIO Pin | Schematic | U?? Pin | Notes |
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RTC
MIO Pin | Schematic | U? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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EEPROM
MIO Pin | Schematic | U?? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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CAN Transceiver
Bank | Schematic | U?? Pin | Notes |
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| D-Tx |
| Driver Input |
| R-Rx |
| Reciever Output |
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Clock Sources
Designator | Description | Frequency | Note |
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| MHz |
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| KHz |
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
U?? Pin
| Signal | Connected to | Direction | Note |
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IN0 |
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| IN1 |
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| IN2 |
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| IN3 |
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| XAXB |
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| SCLK |
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| SDA |
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| OUT0 |
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| OUT1 |
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| OUT2 |
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| OUT3 |
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| OUT4 |
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| OUT5 |
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| OUT6 |
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| OUT7 |
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| OUT8/OUT9 |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
---|
VIN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Voltage Monitor Circuit
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
|
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
---|
| REV01 |
| REV01 |
| REV02 | - Support M2S050 -> added R29,R30, C24..C26,C31
- Added resistor R32
- Full upd LIB
| REV02 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Date | Revision | Contributor | Description |
---|
| | | | -- | all | | |
|
Disclaimer