Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2023-06-133.1.16
  • Design flow:
    • added alternative programming files in Petalinux
  • added chapter FSBL Patch in Software Design - Petalinux
ma
2023-06-013.1.15
  • removed u-boot.dtb from Design flow
ma
2023-06-013.1.14
  • expandable lists for revision history and supported hardware
wh
2023-05-253.1.13
  • updated according to Vivado 2022.2
ma
2023-02-083.1.12
  • removed content of
    • Special FSBL for QSPI programming
ma
2022-08-243.1.11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.scr description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator



Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template (note: inner scroll ignore/only only with drawIO object):


        Create DrawIO object here: Attention if you copy from other page, use


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)


      • ExampleComment
        12



  • ...

Overview


Notes :

Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • Add basic key futures, which can be tested with the design


  • Vitis/Vivado 2022.2
  • PetaLinux 2022.2
  • RF Analyzer 2023.1
  • PCIe (endpoint)
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • Modified FSBL for SI5395 programming
  • Special FSBL for QSPI programming

Revision History

Notes :

  • add every update file on the download
  • add design changes on description

DateVivadoProject BuiltAuthorsDescription
2023-11-092022.2

TE0835-test_board_noprebuilt-vivado_2022.2-build_9_20231109094654.zip
TE0835-test_board-vivado_2022.2-build_9_20231109094654.zip

Mohsen Chamanbaz
  • PCIe endpoint in device tree added.
  • Ethernet phy and usb phy are reset while booting. 
2022-09-212022.2

TE0835-test_board_noprebuilt-vivado_2022.2-build_8_20230921095939.zip
TE0835-test_board-vivado_2022.2-build_8_20230921095939.zip

Mohsen Chamanbaz
  • 2022.2 release
2022-02-242020.2TE0835-test_board_noprebuilt-vivado_2020.2-build_9_20220223123143.zip
TE0835-test_board-vivado_2020.2-build_9_20220223123124.zip		Mohsen Chamanbaz
  • XCZU47DR variant was added.
  • HDL files for XCZU25DR has been updated.
  • RF analyzer software was updated to 2020.2 version.
2022-02-112020.2TE0835-test_board_noprebuilt-vivado_2020.2-build_5_20220211054445.zip
TE0835-test_board-vivado_2020.2-build_5_20220211054430.zip		Mohsen Chamanbaz/John Hartfiel
  • Bugfix, now with  20.2 FSBL
2021-07-142020.2TE0835-test_board_noprebuilt-vivado_2020.2-build_5_20210714111839.zip
TE0835-test_board-vivado_2020.2-build_5_20210714111826.zip		Mohsen Chamanbaz
  • 2020.2 release
2020-10-272019.2

TE0835-test_board_noprebuilt-vivado_2019.2-build_15_20201027100145.zip
TE0835-test_board-vivado_2019.2-build_15_20201027100128.zip

Mohsen Chamanbaz
  • initial release

Release Notes and Know Issues

Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


IssuesDescriptionWorkaroundTo be fixed version
Updating the signal property failed, while the generation of the signal is already in progressIt is difficult to update the property of the generated signal while the generation of the signal by DACs is already running. The Generation button must be clicked several times to make the change in the output.
  • It is recommended to reprogram and initialize the boad again if such situation happens.
Solved with 2022-02-24 update


Requirements

Software

Notes :

  • list of software which was used to generate the design


SoftwareVersionNote
Vitis2022.2needed, Vivado is included into Vitis installation
PetaLinux2022.2needed
RF Analyzer2023.1needed
SI ClockBuilder Pro---optional


Hardware

Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotesDesign
TE0835-02-MXE21-A25dr_1e_4gbREV024GB128MBNANANATE0835
TE0835-02-TXE21-A47dr_1e_4gbREV024GB128MBNANANATE0835

TE0835-02-UXE21-A*

48dr_1e_4gbREV024GB128MBNANANATE0835

TE0835-02-TXI21-A 

47dr_1e_4gbREV024GB128MBNANANATE0835

TE0835-02-TXE21-AS

47dr_1e_4gbREV024GB128MBNANANATE0835

TE0835-01-MXE21-A 

25dr_1e_4gbREV014GB128MBNANANATE0835

TE0835-02-S001    

47dr_1e_4gbREV024GB128MBNANANATE0835

TE0835-02-S002    

47dr_1e_4gbREV024GB128MBNANANATE0835
TE0835-02-S00425dr_1e_4gbREV024GB128MBNANANATE0835

*used as reference


Design supports following carriers:

Carrier ModelNotes
TEB0835-02*

*used as reference

Additional HW Requirements:

Additional HardwareNotes
Micro USB Cable for JTAG/UART
Cooler

It is strongly recommended that the RFSoC should  be used with heat sink.

SMA male connector cableSome ADC inputs/DAC outputs have the SMA connector
UFL female connector cableSome ADC inputs/DAC outputs have the UFL connector
Ethernet cable
SD card16GB
Signal generator (optional)To feed a desired signal to the input of ADC
Oscilloscope (optional)To monitor the output signal of DACs.
PCWith ATX Power supply and PCIe X8 slot


Content

Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib		Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

TypeLocationNotes
SI5395 (PLL of the RFSoc Module)<design name>/misc/Si5395SI5395 Project with current PLL Configuration
SI5395 (PLL of the carrier board)<design name>/misc/Si5395SI5395 Project with current PLL Configuration
init.sh<project folder>\misc\sd\Additional Initialization Script for Linux


Prebuilt

Notes :

  • prebuilt files
  • Template Table:


    • File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems








File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynqmp RFSoC-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynqmp RFSoC or MicroBlaze Processor Systems
Clock Builder Pro project file*.slabtimeprojDefines the necessary clock frequencies for the PLLs on the RFSoC module and carrier board


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Software Setup

Download RF Analyzer GUI from the following link and install it.

Design Flow


Notes :

  • Basic Design Steps

  • Add/ Remove project specific description


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    ------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0)  Module selection guide, project creation...prebuilt export...
-- (1)  Create minimum setup of CMD-Files and exit Batch
-- (2)  Create maximum setup of CMD-Files and exit Batch
-- (3)  (internal only) Dev
-- (4)  (internal only) Prod
-- (c)  Go to CMD-File Generation (Manual setup)
-- (d)  Go to Documentation (Web Documentation)
-- (g)  Install Board Files from Xilinx Board Store (beta)
-- (a)  Start design with unsupported Vivado Version (beta)
-- (x)  Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.

    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"


      Note: Select correct one, see also Vivado Board Part Flow


  4. Create hardware description file (.xsa file) for petaLinux project and export to prebuilt folder

    TE::hw_build_design -export_prebuilt


    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"

    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
  7. Generate Programming Files with Vitis (recommended)
    1. Copy PetaLinux build image files to prebuilt folder 

      • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


        This step depends on Xilinx Device/Hardware

        For 2020.2 :

        for Zynq-7000 series

        • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ZynqMP

        • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ...

        • ...

        For 2021.2 :

        This step depends on Xilinx Device/Hardware

        for Zynq-7000 series

        • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ZynqMP

        • copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for Microblaze

        • ...


    2. Generate Programming Files with Vitis

      TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


  8. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch


Note:

  • Programming and Startup procedure

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection

    3. Select Create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

      Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module

  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    TE::pr_program_flash -swapp u-boot
TE::pr_program_flash -swapp hello_te0835 (optional)


    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup


  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub and Boot.bin on SD-Card
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Hardware Setup

The Hardware contains of a TE0835 module and TEB0835 carrier board and has 8 ADC inputs and 8 DAC outputs.

  1. Plug the TE0835 module on the TEB0835 carrier board
  2. Install the cooler on the RFSoC chip
    1. Attention: It is strongly recommended that the RFSoC should not be used without heat sink.
  3. Connect the micro USB cable to the J29 connector
  4. Plug the board on the PCIe port of the PC
  5. Plug the prepared SD card on the SD card socket (J28)
  6. Connect a cable with SMA or UFL connector to one of the DAC connector( for example DAC0 J9) and feed it back to the related ADC input (for example ADC0 J1)
  7. (optional) A signal generator can be used to feed desired sinal to ADC input.
  8. (optional) An oscilloscope can be used to monitor the output signal of DAC.

Usage

  1. Prepare HW like described on section Hardware Setup
  2. Connect UART USB (most cases same as JTAG)

  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.


    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr


  4. Power On PCB

    1. Zynqmp RFSoC Boot ROM loads FSBL from SD into OCM

    2. FSBL loads U-boot from SD into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for ZynqMP???

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for Microblaze with Linux

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


    for native FPGA

    ...


Linux

  1. Open Serial Console (e.g. putty)
    • Speed: 115200

    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


  2. Linux Console:

    # password disabled
petalinux login: root
Password: root

     

    Note: Wait until Linux boot finished


  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C Bus; BUS 0 up to 5 possible)
dmesg | grep rtc	(RTC check)
udhcpc				(ETH0 check)
lsusb				(USB check)


  4. Option Features
    • Webserver to get access to Zynqmp RFSoC
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado HW Manager

Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequency...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Monitoring:
    • The output frequency  of MMCM blocks can be monitored.
      • Set radix from VIO signals to unsigned integer.
      • The temperature of ARM processor and FPGA can be measured too.


RF Analyzer

  1. Open the RF Analyzer GUI
  2. Click on Connect button
  3. Adjust the desired JTAG frequency (for example 30MHZ)
  4. Give the generated bitstream file path
  5. Click on Download Bitstream button to load the Bitstream file on the FPGA
  6. When downloading is finished, click on Select Target button
  7. After initialisation, all ADCs/DACs tiles are visible
  8. Click on desired DAC tile and choose a DAC (for example DAC0)
  9. Adjust desired DAC properties (for example output frequency)
  10. Click on Generate button to generate the signal in output of DAC
  11. Click on the related ADC tile and choose the related ADC (for example ADC0)
  12. Click on Acquire button to acquire the input signal
  13. The spectrum of the DAC output signal can be seen now. The signal can be visible in time domain too.
    1. Tip: In menu Window click on Multi view to see all of DACs and ADCs simultaneously.


RF Analyzer GUIBoard TE0835 ( RFSoC U1)
TEB0835
Tile /ConverterSoC Pin NameSoC Pin NumberB2BSignal NameConnector DesignatorConnector Type
ADC Tile 0-ADC 01ADC0_P/ADC0_NAK2/AK131/29ADC0_P/ADC0_NJ1SMA
ADC Tile 0-ADC 23ADC1_P/ADC1_NAH2/AH143/41ADC1_P/ADC1_NJ2UFL
ADC Tile 1-ADC 01ADC2_P/ADC2_NAF2/AF149/47ADC2_P/ADC2_NJ3SMA
ADC Tile 1-ADC 23ADC3_P/ADC3_NAD2/AD159/61ADC3_P/ADC3_NJ4UFL
ADC Tile 2-ADC 01ADC4_P/ADC4_NAB2/AB167/65ADC4_P/ADC4_NJ5SMA
ADC Tile 2-ADC 23ADC5_P/ADC5_NY2/Y179/77ADC5_P/ADC5_NJ6UFL
ADC Tile 3-ADC 01ADC6_P/ADC6_NV2/V185/83ADC6_P/ADC6_NJ7SMA
ADC Tile 3-ADC 23ADC7_P/ADC7_NT2/T197/95ADC7_P/ADC7_NJ8UFL
DAC Tile 0-DAC 0DAC0_P/DAC0_NN2/N1103/101DAC0_P/DAC0_NJ9SMA
DAC Tile 0-DAC 1DAC1_P/DAC1_NL2/L1109/107DAC1_P/DAC1_NJ10UFL
DAC Tile 0-DAC 2DAC2_P/DAC2_NJ2/J1121/119DAC2_P/DAC2_NJ11SMA
DAC Tile 0-DAC 3DAC3_P/DAC3_NG2/G1127/125DAC3_P/DAC3_NJ12UFL
DAC Tile 1-DAC 0DAC4_P/DAC4_NE2/E1133/131DAC4_P/DAC4_NJ13UFL
DAC Tile 1-DAC 1DAC5_P/DAC5_NC2/C1139/137DAC5_P/DAC5_NJ14UFL
DAC Tile 1-DAC 2DAC6_P/DAC6_NB4/A4151/149DAC6_P/DAC6_NJ15UFL
DAC Tile 1-DAC 3DAC7_P/DAC7_NB6/A6157/155DAC7_P/DAC7_NJ16UFL




RF Analyzer GUIBoard TE0835 ( RFSoC U1)
TEB0835
Tile /ConverterSoC Pin NameSoC Pin NumberB2BSignal NameConnector DesignatorConnector Type
ADC Tile 0-ADC 01ADC0_P/ADC0_NAK2/AK131/29ADC0_P/ADC0_NJ1SMA
ADC Tile 0-ADC 23ADC1_P/ADC1_NAH2/AH143/41ADC1_P/ADC1_NJ2UFL
ADC Tile 1-ADC 01ADC2_P/ADC2_NAF2/AF149/47ADC2_P/ADC2_NJ3SMA
ADC Tile 1-ADC 23ADC3_P/ADC3_NAD2/AD159/61ADC3_P/ADC3_NJ4UFL
ADC Tile 2-ADC 01ADC4_P/ADC4_NAB2/AB167/65ADC4_P/ADC4_NJ5SMA
ADC Tile 2-ADC 23ADC5_P/ADC5_NY2/Y179/77ADC5_P/ADC5_NJ6UFL
ADC Tile 3-ADC 01ADC6_P/ADC6_NV2/V185/83ADC6_P/ADC6_NJ7SMA
ADC Tile 3-ADC 23ADC7_P/ADC7_NT2/T197/95ADC7_P/ADC7_NJ8UFL
DAC Tile 0-DAC 0DAC0_P/DAC0_NN2/N1103/101DAC0_P/DAC0_NJ9SMA
DAC Tile 0-DAC 2DAC1_P/DAC1_NL2/L1109/107DAC1_P/DAC1_NJ10UFL
DAC Tile 1-DAC 0DAC2_P/DAC2_NJ2/J1121/119DAC2_P/DAC2_NJ11SMA
DAC Tile 1-DAC 2DAC3_P/DAC3_NG2/G1127/125DAC3_P/DAC3_NJ12UFL
DAC Tile 2-DAC 0DAC4_P/DAC4_NE2/E1133/131DAC4_P/DAC4_NJ13UFL
DAC Tile 2-DAC 2DAC5_P/DAC5_NC2/C1139/137DAC5_P/DAC5_NJ14UFL
DAC Tile 3-DAC 0DAC6_P/DAC6_NB4/A4151/149DAC6_P/DAC6_NJ15UFL
DAC Tile 1-DAC 2DAC7_P/DAC7_NB6/A6157/155DAC7_P/DAC7_NJ16UFL



As an example the GUi should be seen after initialization as below:



For example, when all DACs are in operation, the GUI can be seen as below:

For example, when all ADCs are in operation, the GUI can be seen as below:

System Design - Vivado


Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design




PS Interfaces

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

TypeNote
DDR
QSPIMIO
SD1MIO
I2C0MIO
I2C1MIO
UART0MIO
GPIO0MIO
GPIO1MIO
GPIO2MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO
PCIeMIO


Constraints

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain


set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/F_reg[*]/D}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_A_B_DATA_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_ALU_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_OUTPUT_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_C_DATA_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[4].COUNTER_F_inst/bl.DSP48E_2/DSP_ALU_INST/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[4].COUNTER_F_inst/bl.DSP48E_2/DSP_OUTPUT_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[5].COUNTER_F_inst/bl.DSP48E_2/DSP_ALU_INST/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[5].COUNTER_F_inst/bl.DSP48E_2/DSP_OUTPUT_INST/*}]


#----------------------------------------------------------------------
# Title      : Example top level constraints for UltraScale+ RF Data Converter
#----------------------------------------------------------------------
# File       : usp_rf_data_converter_0_example_design.xdc
#----------------------------------------------------------------------
# Description: Xilinx Constraint file for the example design for
#              UltraScale+ RF Data Converter core
#---------------------------------------------------------------------
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
# 
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
# 
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES. 
#
#---------------------------------------------------------------------

#------------------------------------------
# TIMING CONSTRAINTS
#------------------------------------------
# Set AXI-Lite Clock to 100MHz
#create_clock -period 10.000 -name usp_rf_data_converter_0_axi_aclk [get_pins axi_aclk_i/CFGMCLK]

# ADC Reference Clock for Tile 0 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc0_clk [get_ports adc0_clk_p]

# ADC Reference Clock for Tile 1 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc1_clk [get_ports adc1_clk_p]

# ADC Reference Clock for Tile 2 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc2_clk [get_ports adc2_clk_p]

# ADC Reference Clock for Tile 3 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc3_clk [get_ports adc3_clk_p]

# DAC Reference Clock for Tile 0 running at 307.200 MHz
create_clock -period 3.255 -name usp_rf_data_converter_0_dac0_clk [get_ports dac0_clk_p]

# DAC Reference Clock for Tile 1 running at 307.200 MHz
create_clock -period 3.255 -name usp_rf_data_converter_0_dac1_clk [get_ports dac1_clk_p]

set_multicycle_path -to [get_pins -filter {REF_PIN_NAME== D} -of [get_cells -hier -filter {name =~ *usp_rf_data_converter_0_ex_i/ex_design/usp_rf_data_converter_0/inst/IP2Bus_Data_reg*}]] -setup 2
set_multicycle_path -to [get_pins -filter {REF_PIN_NAME== D} -of [get_cells -hier -filter {name =~ *usp_rf_data_converter_0_ex_i/ex_design/usp_rf_data_converter_0/inst/IP2Bus_Data_reg*}]] -hold 1
###############################################################################
# False paths
# For debug in synth use
# report_timing_summary -setup -slack_lesser_than 0
###############################################################################
# Data generator/capture constraints
set rfa_from_list   [get_cells -hier -regexp .*rf(?:da|ad)c_exdes_ctrl_i\/(?:da|ad)c_exdes_cfg_i\/.+num_samples_reg.*]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_00*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_00*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_01*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_01*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_02*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_02*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_03*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_03*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_10*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_10*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_11*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_11*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_12*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_12*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_13*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_13*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_from_list   [get_cells -hier -regexp .*rf(?:da|ad)c_exdes_ctrl_i\/(?:da|ad)c_exdes_cfg_i\/.+num_samples_reg.*]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
  




set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/F_reg[*]/D}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_A_B_DATA_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_ALU_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_OUTPUT_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_C_DATA_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[4].COUNTER_F_inst/bl.DSP48E_2/DSP_ALU_INST/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[4].COUNTER_F_inst/bl.DSP48E_2/DSP_OUTPUT_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[5].COUNTER_F_inst/bl.DSP48E_2/DSP_ALU_INST/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[5].COUNTER_F_inst/bl.DSP48E_2/DSP_OUTPUT_INST/*}]


#----------------------------------------------------------------------
# Title      : Example top level constraints for UltraScale+ RF Data Converter
#----------------------------------------------------------------------
# File       : usp_rf_data_converter_0_example_design.xdc
#----------------------------------------------------------------------
# Description: Xilinx Constraint file for the example design for
#              UltraScale+ RF Data Converter core
#---------------------------------------------------------------------
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
# 
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
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# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
# 
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES. 
#
#---------------------------------------------------------------------

#------------------------------------------
# TIMING CONSTRAINTS
#------------------------------------------
# Set AXI-Lite Clock to 100MHz
create_clock -period 10.000 -name usp_rf_data_converter_0_axi_aclk [get_pins axi_aclk_i/CFGMCLK]

# ADC Reference Clock for Tile 0 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc0_clk [get_ports adc0_clk_p]

# ADC Reference Clock for Tile 1 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc1_clk [get_ports adc1_clk_p]

# ADC Reference Clock for Tile 2 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc2_clk [get_ports adc2_clk_p]

# ADC Reference Clock for Tile 3 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc3_clk [get_ports adc3_clk_p]

# DAC Reference Clock for Tile 0 running at 307.200 MHz
create_clock -period 3.255 -name usp_rf_data_converter_0_dac0_clk [get_ports dac0_clk_p]

set_multicycle_path -to [get_pins -filter {REF_PIN_NAME== D} -of [get_cells -hier -filter {name =~ *usp_rf_data_converter_0_ex_i/ex_design/usp_rf_data_converter_0/inst/IP2Bus_Data_reg*}]] -setup 2
set_multicycle_path -to [get_pins -filter {REF_PIN_NAME== D} -of [get_cells -hier -filter {name =~ *usp_rf_data_converter_0_ex_i/ex_design/usp_rf_data_converter_0/inst/IP2Bus_Data_reg*}]] -hold 1
###############################################################################
# False paths
# For debug in synth use
# report_timing_summary -setup -slack_lesser_than 0
###############################################################################
# Data generator/capture constraints
set rfa_from_list   [get_cells -hier -regexp .*rf(?:da|ad)c_exdes_ctrl_i\/(?:da|ad)c_exdes_cfg_i\/.+num_samples_reg.*]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_00*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_00*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_00*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_00*addrbend_reg}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_02*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_02*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_02*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_02*addrbend_reg}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_10*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_10*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_10*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_10*addrbend_reg}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_12*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_12*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_12*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_12*addrbend_reg}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_20*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_20*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_20*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_20*addrbend_reg}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_22*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_22*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_22*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_22*addrbend_reg}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_30*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_30*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_30*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_30*addrbend_reg}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_32*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_32*addrb_reg[*]}]]]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_32*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*dg_slice_32*addrbend_reg}]]]
set rfa_from_list   [get_cells -hier -regexp .*rf(?:da|ad)c_exdes_ctrl_i\/(?:da|ad)c_exdes_cfg_i\/.+num_samples_reg.*]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_00*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_00*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_00*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_00*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_01*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_01*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_01*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_01*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_02*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_02*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_02*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_02*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_03*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_03*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_03*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_03*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_10*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_10*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_10*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_10*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_11*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_11*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_11*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_11*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_12*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_12*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_12*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_12*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_13*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_13*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_13*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_13*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_20*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_20*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_20*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_20*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_21*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_21*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_21*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_21*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_22*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_22*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_22*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_22*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_23*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_23*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_23*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_23*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_30*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_30*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_30*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_30*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_31*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_31*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_31*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_31*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_32*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_32*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_32*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_32*wea_r_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_33*addra_reg[*]}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_33*working_i_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_33*cap_complete_reg}]]]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
create_waiver -user USP_RF_DATA_CONVERTER -type CDC -id CDC-1 \
  -description "Number of samples register is a constant during normal operation" \
  -from [list [get_pins -filter {REF_PIN_NAME=~*} -of [get_cells -hier -filter {name=~*c_exdes_cfg_i*num_samples_reg*}]]] \
  -to   [list [get_pins -filter {REF_PIN_NAME==D} -of [get_cells -hier -filter {name=~*ds_slice_33*wea_r_reg}]]]
    


Software Design - Vitis


Note:

  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2022.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2022.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2022.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY


----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2022.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2022.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5395 on the TE0835 RFSoC module configuration
    • Si5395 on the TEB0835 carrier board configuration

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0835

Hello TE0835 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

Software Design -  PetaLinux


Note:

  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

Select SD as default:

  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

Add new flash partition for bootscr and sizing:

  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000

Identification:

  • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
  • CONFIG_SUBSYSTEM_PRODUCT="TE0835"

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

  • CONFIG_I2C_EEPROM=y

  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

  • CONFIG_SYS_I2C_EEPROM_ADDR=0

  • CONFIG_SYS_I2C_EEPROM_BUS=0

  • CONFIG_SYS_EEPROM_SIZE=256

  • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

  • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

  • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

  • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

MAC from eeprom together with uboot and device tree settings:

  • CONFIG_ENV_OVERWRITE=y
  • CONFIG_NET_RANDOM_ETHADDR is not set

Boot Modes:

  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_IN_FAT is not set
  • CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_ENV_IS_IN_SPI_FLASH is not set
  • CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000

Identification

  • CONFIG_IDENT_STRING="TE0835"

Change platform-top.h:

Device Tree
/include/ "system-conf.dtsi"
/ {
	chosen {
		xlnx,eeprom = &eeprom;
	};
};
 
 
 #include "include/dt-bindings/phy/phy.h"
 
/*------------------ SD --------------------*/ 
/* SDIO */
 
&sdhci1 {
	disable-wp;
	no-1-8-v;
};

/*------------------ ETH PHY --------------------*/ 
/* ETH PHY */
&gem3 { 
	status = "okay";
	ethernet_phy0: ethernet-phy@0 {
		compatible = "marvell,88e1510";
		device_type = "ethernet-phy";
		reg = <1>;
	};
};

/*------------------- USB --------------------*/
/* USB 2.0 */
  
/* USB  */
&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	maximum-speed = "high-speed";
	/delete-property/phy-names;
	/delete-property/phys;
	/delete-property/snps,usb3_lpm_capable;
	snps,dis_u2_susphy_quirk;
	snps,dis_u3_susphy_quirk;
};
    
&usb0 {
	status = "okay";
	// /delete-property/ clocks;
	// /delete-property/ clock-names;
	//clocks = <0x3 0x20>;
	//clock-names = "bus_clk";
};
 
/*-------------------- QSPI ---------------------*/ 
/* QSPI PHY */
&qspi {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	flash0: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

/*------------------ I2C --------------------*/
 
// This I2C Port can be found in the RFSoC Module TE0835 to control PLL chip SI5395A-A-GM on the
// RFSoC Module.
 
&i2c1 {
	eeprom: eeprom@50 {
		//compatible = "atmel,24c08";
		compatible = "microchip,24aa025", "atmel,24c02";
		reg = <0x50>;
	};
};
 
// This I2C Port connects RFSoC FPGA on the RFSoC Module and I2C multiplexer Chip on the carrier
// board through B2B connector. 
 
&i2c0 {
 
	// This I2C multiplexer chip can be found in TEB0835 carrier board.

	i2c_mux@70 { 										/* TCA9544APWR U7 in the carrier board TEB0835 */
		compatible = "nxp,pca9544";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 { 										/* FireFly_B*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		i2c@1 { 										/* FireFly_A*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		i2c@3 { 										/* LM96163CISD/NOPB U9 FAN Controller in the carrier board TEB0835*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			temp@4c {									/* lm96163 - u9*/
				compatible = "national,lm96163";
				reg = <0x4c>;
			};
		};
		i2c@4 { 										/* SI5395A-A-GM U5 DPLL in the carrier board TEB0835*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			clock-generator@68{							/* SI5395A-A-GM U5 DPLL in the carrier board TEB0835 */
				compatible = "silabs,si5395";
				reg = <0x68>;
			};
		};
	};
};

/*------------------ PCIe --------------------*/

/ {
  refclk3:psgtr_dp_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <27000000>;
  };

  refclk2:psgtr_pcie_usb_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <100000000>;
  };

  refclk1:psgtr_sata_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <150000000>;
  };

};

&psgtr {
       status = "okay";
       #clock-cells = <0x01>;
       clocks = <&refclk2>;
       clock-names = "ref2";
};

&pcie {
      status = "okay";
      phy-names="pciephy";
      phys = <&psgtr 0x0 PHY_TYPE_PCIE 0x0 0x0>;

};

     
Kernel
Start with petalinux-config -c kernel
Changes:
  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
  • CONFIG_EDAC_CORTEX_ARM64=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
  • CONFIG_auto-login=y
  •  CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"
FSBL patch (alternative for vitis fsbl trenz patch)
  • Hint only needed for series with different PLL versions.
  • adjust name for PLL files (SI...)
for Zynq-7000 series 
te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynq_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynq_fsbl\src"

for ZynqMP???
te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"

for Microblaze with Linux
...

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"

Applications
See: "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application accemble for Zynqmp RFSoC access. Need busybox-httpd
Additional Software

Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:
No additional software is needed.
SI5395 of RFSoC module
File location <design name>/misc/Si5395/Si5395-*-835-*.slabtimeproj
General documentation how you work with these project will be available on Si5395
SI5395 of carrier board
File location <design name>/misc/Si5395/Si5395-*-B835-*.slabtimeproj
General documentation how you work with these project will be available on Si5395
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision  got to "Change History"  of this page and select older document revision number.
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first
    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
    • Metadata is only used of compatibility of older exports

DateDocument Revision
Authors
Description
  • correction download Link to 22.2 version
2023-11-09
v.35
Mohsen Chamanbaz
  • PCIe endpoint in device tree added.
  • Ethernet phy and usb phy are reset while booting. 
2023-09-21
v.34
Mohsen Chamanbaz
  • Release 2022.2
2023-08-07
v.33
Mohsen Chamanbaz
  • Document adapted
2022-02-24v.31Mohsen Chamanbaz
  • Design Update
  • Documentation Update
  • XCZU47DR variant was added.
  • HDL files for XCZU25DR has been updated.
  • RF analyzer software was updated to 2020.2 version.
2022-02-11v.28John Hartfiel
  • Bugfix design
2021-07-14v.27John Hartfiel
  • Release 2020.2
2020-12-09v.25John Hartfiel
  • Style changes
  • additional notes
2020-11-02v.20Mohsen Chamanbaz
  • Release 2019.2
--all
--

Legal Notices
















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