Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TE0716 is a commercial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020, with 1GB of DDR3L-1600 SDRAM, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages.
Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC/FPGA
- Package: SFVC784
- Device: Xilinx Z-7020
- Speed: -1
- Temperature: C grade.
- Xilinx XC7Z020 SoC:
- Processing system (PS):
- ARM® CortexTM-A9 MPCoreTM with CoreSightTM.
- L1 Cache: 32KB Instruction, 32KB Data per processor.
- L2 Cache: 512KB.
- Programmable logic (PL):
- Artix-7 FPGA Equivalent.
- Logic cells: 85K.
- Look-Up Tables: 53200.
- Block RAM: 4.9 Mb.
- DSP slices: 220.
- Peak DSP performance: 276 GMACs.
- 2x 12 bit, 1 MSPS ADCs with up to 17 Differential Inputs.
- 120 x PL HR I/O (48 differential pairs and 24 single-ended).
- 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
- 1GByte DDR3L SDRAM memory (2 x [256Mbit x 16]), 32-bit wide data bus.
- 32MByte Quad SPI Flash memory.
- MAC address serial EEPROM with EUI-48TM node identity (24AA025E48).
- 512Kb Serial EEPROM memory (CAT24C512).
- 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
- Gigabit Ethernet transceiver PHY (Marvell 88E1512).
- Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK).
- Single chip USB Interface 2.0 High Speed 480Mbs to UART / JTAG(Xilinx License included) (FTDI FT2232H-56Q), including microUSB-B connector.
- 2xUser RGB LEDs (Green), LED FPGA DONE (Green).
- 2 x Tactile Switches (User), 1 x Tactile Switche (Reset).
- Card Connector microSD™.
- On-board high-efficiency DC-DC converters for all voltages used.
- Board Size: 65 x 45 mm.
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Xilinx Zynq XC7Z SoC, U5
- 4Gbit DDR3/L SDRAM, U13
- 4Gbit DDR3/L SDRAM, U12
- 32MByte Quad SPI Flash memory, U7
- 2Kbit MAC address serial EEPROM with EUI-48TM node identity, U24
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | IC Designator | Content | Notes |
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Quad SPI Flash | U7 | Empty | - | 512Kb Serial EEPROM | U21 | Empty | - | 2Kb 24AA025E48 EEPROM | U24 | Pre-programmed globally unique, 48-bit node address (MAC). | - | 4Kb M93C66-R EEPROM | U40 | Xilinx JTAG Programmer License | - |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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Boot process.
The TE0716 supports QSPI and SD Card boot modes, which is controlled by the insertion of the SD card before powering on.
SD Card State | Boot Mode | Notes |
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SD card inserted | SD Card (J2) | - | SD card not present | QSPI (U7) | - |
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Reset process.
The nRST signal active low reset input, forces PS_POR_B to apply a master reset of the entire Zynq. This reset could be manually done by pressing a switch. This signal could be also reached by a B2B large connector.
This nRST signal (active low) is also held until all FPGA power supplies set their Power Good signals.
Furthermore, if the FPGA core voltage drops under 0.84V or the 3.3V power supply drops to 2.94V or less, this nRST signal is also activated by the Voltage Monitor.
See more about the Power-on Reset (PS_POR_B) signal in the “Zynq-7000 SoC Technical Reference Manual” (“UG585”).
Signal | B2B | I/O | Note |
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nRST | JP2-4 | - | - | nRST | - | S3 | - |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
Zynq SoC's I/O banks signals connected to the B2B connectors:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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MIO 500 | JP1 | 2 | 3.3V | - | HR 35 | JP1 | 48 | 3.3V | - | HR 13 | JP2 | 50 | 3.3V | - | HR 33 | JP2 | 22 | 3.3V | - |
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
JTAG Signal | B2B Connector |
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TMS | JP2-7 | TDI | JP2-11 | TDO | JP2-10 | TCK | JP2-8 |
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MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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MIO Pin | Connected to | B2B | Notes |
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15 | UART_TX_ZYNQ | JP1-70 | Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High". | 14 | UART_RX_ZYNQ | JP1-71 | Also Connected to U36-3. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High". |
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Test Points
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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Test Point | Signal | Connected to | Notes |
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TP1 | +1.0V |
| - | TP2 | ADC_VAA |
| - | TP3 | +1.5V |
| - | TP4 | +1.8V |
| - | TP5 | VTT |
| - | TP6 | VTTREF |
| - | TP7 | +5.0V |
| - | TP8 | +3.3V |
| - | TP9 | +5.0V_VAA |
| - | TP10 | +3.3V_ADC |
| - | TP11 | GND |
| - | TP12 | GND |
| - | TP13 | SPI-DQ3/M0 |
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| TP14 | GND |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
On-board 32MByte QSPI flash memory S25FL256S (U7) could be used to store the initial FPGA configuration file. After configuration completes, the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
- Part number: S25FL256SAGBHI20
- Supply voltage: 3.3V (2.7V - 3.6V).
- Speed: 133MHz max.
- Temperature: Industrial Range -40°C to +85°C.
MIO Pin | Schematic | U7 Pin | Notes |
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ADCs
The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.
- Part number: NCD98011XMXTAG
- Analog supply and ADC reference voltage: 3.3V (1.65V – 3.6V).
- Digital I/O supply voltage: 3.3V (1.65V – 3.6V).
- Differential analog inputs: 1 per ADC.
- Sampling rate: 2 MSPS max.
- SNR: 70dB @1KHz fIN.
- THD: -80dB @1KHz fIN.
- Junction Temperature: Range -40°C to +125°C.
MIO Pin | Schematic | U? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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EEPROM
MAC-Address EEPROM
A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.
- Part number: 24AA025E48T-I/OT
- Supply voltage: 1.8V (1.7V - 5.5V).
- FCLK: 100KHz (@VCC=1.8V)
- Temperature: Industrial Range -40°C to +85°C.
MIO Pin | Schematic | U?? Pin | Notes |
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General Purpose EEPROM
- The TE0716 module has also a 512Kb Serial EEPROM I2C memory (U21).
- Part number: CAT24C512WI-GT3
- Supply voltage: 1.8V (1.8V - 5.5V).
- FCLK: 100KHz/400KHz/1MHz
- Temperature: Industrial Range -40°C to +85°C.
I2C Device | I2C Address | Designator | Notes |
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2K Serial EEPROMs with EUI-48™ | 0xA6 (write) 0xA7 (read) 0x53 (7bit) | U24 |
| 512Kb Serial EEPROM | 0xA0 (write) 0xA1 (read) 0x50 (7bit) | U21 |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0716 module has two 500MByte DDR3L SDRAM chips (U12 & U13) arranged into 32-bit wide memory bus providing total on-board memory size of 1GByte.
- Part number: IS43TR16256BL-125KBLI
- Configuration: 256Mx16.
- Supply voltage: 1.35V (1.5V tolerant).
- Speed: 1.25ns @ CL11 (DDR3-1600)
- Temperature: Industrial Range -40°C to +95°C Tcase.
Ethernet
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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CAN Transceiver
Bank | Schematic | U?? Pin | Notes |
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| D-Tx |
| Driver Input |
| R-Rx |
| Reciever Output |
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Clock Sources
Designator | Description | Frequency | Note |
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
U?? Pin
| Signal | Connected to | Direction | Note |
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IN0 |
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| SCLK |
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| SDA |
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| OUT0 |
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| OUT1 |
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| OUT2 |
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| OUT3 |
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| OUT4 |
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| OUT5 |
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| OUT6 |
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| OUT7 |
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| OUT8/OUT9 |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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Power-On Sequence
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Voltage Monitor Circuit
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Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
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Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
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Date | Revision | Contributor | Description |
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