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Overview

The Trenz Electronic TE0716 is a commercial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020, with 1GB of DDR3L-1600 SDRAM, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, an USB PHY transceiver, a single chip USB 2.0 to UART/JTAG Interface (Xilinx License included), and powerful switching-mode power supplies for all on-board voltages.

Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.

Key Features

• SoC/FPGA
  
  • Package: CLG484
  • Device: Xilinx Z-7020
  • Speed: -1 *
  • Temperature: C grade *.
• RAM/Storage
  • Low Power DDR3 SDRAM on PS
    • Data width: 32bit
    • Size: def. 1GB *
    • Speed: 1600 Mbps **
  • QSPI boot Flash
    • Data width: 4bit
    • size: 32MB *
  • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48).
  • 512Kb user MAC address serial EEPROM.
• On Board
  
  • 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
  • Low Power Oscillators.
  • Gigabit Ethernet PHY transceiver (Marvell Alaska 88E1512).
  • High-Speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C).
  • Single chip High-Speed USB 2.0 to UART/JTAG Interface (Xilinx License included) (FTDI FT2232H).
  • 2xUser RGB LEDs (Green), LED FPGA "Done" (Green).
  • 2 x Tactile Switches (User), 1 x Tactile Switche (Reset).
• Interface
  • 120 x HR PL I/Os (3 banks).
  • 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
  • 1 Gbps RGMII Ethernet interface.
  • High Speed USB 2.0 ULPI with full OTG support.
  • High Speed USB 2.0 to UART/JTAG interface, including microUSB-B connector.
  • microSD™
  • JTAG

• Power
  
  • On-board high-efficiency DC-DC converters for all voltages used.
• Dimension
  • 65 x 45 mm
• Notes
  • * depends on assembly version
  • ** depends on used Zynq and DDR3 combination

Block Diagram

Main Components

1. Xilinx Zynq XC7Z SoC, U5 (Top)
2. 4Gbit DDR3/L SDRAM, U13 (Top)
3. 4Gbit DDR3/L SDRAM, U12 (Top)
4. 32MByte Quad SPI Flash memory, U7 (Top)
5. 2Kbit MAC address serial EEPROM with EUI-48TM node identity, U24 (Top)
6. 512Kb Serial EEPROM memory, U21 (Top)
7. 10x 12-Bit Low Power SAR ADCs, U1..U4, U10, U11, U15..U17, U19 (Top)
8. High-speed USB 2.0 ULPI transceiver, U18 (Top)
9. Single chip USB Interface 2.0 to UART / JTAG, U39 (Top)
10. MicroUSB-B connector, J13 (Top)
11. Low-power oscillator @ 12.000000MHz (OSCI-FTDI), U41 (Top)
12. Low-power oscillator @ 25.000000MHz (ETH-CLK), U9 (Top)
13. LED FPGA "Done" (Green) D3 (Top)
14. User RGB LED 1 D4 (Top)
15. User RGB LED 2 D5 (Top)
16. Tactile Switch (User), S1 (Top)
17. Tactile Switch (User), S2 (Top)
18. Tactile Switch (Reset), S3 (Top)
19. 5A Synchronous Buck DC-DC Converter (1V), U37 (Top)
20. 2A Synchronous Buck DC-DC Converter (3.3V), U46 (Top)
21. 2A Synchronous Buck DC-DC Converter (1.8V), U45 (Top)
22. 2A Synchronous Buck DC-DC Converter (1.5V), U43 (Top)
23. 250mA Ultra-Low Noise LDO Regulator (3.3V_ADC Digital I/O supply), U23 (Top)
24. 250mA Ultra-Low Noise LDO Regulator (ADC_VAA Analog supply/reference, 3.3V), U38 (Top)
25. Gigabit Ethernet PHY transceiver, U8 (Bottom)
26. Low-power oscillator @ 33.333333MHz (PS-CLK), U6 (Bottom)
27. 3A Sink/Source DDR Termination Regulator (VTT/VTTREF, 0.75V), U47 (Bottom)
28. Card Connector microSD™, J2 (Bottom)
29. 2x60 positions high speed/density plug connector, JP1 (Bottom)
30. 2x60 positions high speed/density plug connector, JP2 (Bottom)

Initial Delivery State

Configuration Signals

Boot process.

The TE0716 supports QSPI and SD Card boot modes, which is controlled by the insertion of the SD card before powering on.

Reset process.

The nRST signal active low reset input, forces PS_POR_B to apply a master reset of the entire Zynq. This reset could be manually done by pressing a switch. This signal could be also reached by a B2B large connector.

This nRST signal (active low) is also held until all FPGA power supplies set their Power Good signals.

Furthermore, if the FPGA core voltage drops under 0.84V or the 3.3V power supply drops to 2.94V or less, this nRST signal is also activated by the Voltage Monitor.

See more about the Power-on Reset (PS_POR_B) signal in the “Zynq-7000 SoC Technical Reference Manual” (“UG585”).

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq SoC's I/O banks signals connected to the B2B connectors:

JTAG Interface

JTAG access to the TE0716 SoM through B2B connector JP2.

MIO Pins

PS MIO bank 500 signal connections to B2B JP1 connector, and PS MIO bank 501 signal connections to the microSD™ card J2:

Test Points

On-board Peripherals

DDR3 SDRAM

The TE0716 module has two 500MByte DDR3L SDRAM chips (U12 & U13) fully connected to PS DDR BANK 502, and arranged into 32-bit wide memory bus providing total on-board memory size of 1GByte.

• Configuration: 256Mx16*
• Supply voltage: 1.35V (1.5V tolerant).
• Speed: 1.25ns @ CL11 (DDR3-1600)*
• Temperature: Industrial Range -40°C to +95°C Tcase.

Notes: * standard value but depends on assembly version.

Quad SPI Flash Memory

On-board 32MByte QSPI flash memory S25FL256S (U7) could be used to store the initial FPGA configuration file. After configuration completes, the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

• Part number: S25FL256SAGBHI20
• Supply voltage: 3.3V (2.7V - 3.6V).
• Speed: 133MHz max.
• Temperature: Industrial Range -40°C to +85°C.

EEPROM

There are 2x EEPROMs sharing the same I2C bus:

MAC-Address EEPROM

A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.

• Part number: 24AA025E48T-I/OT
• Supply voltage: 1.8V (1.7V - 5.5V).
• FCLK: 100KHz (@VCC=1.8V)
• Temperature: Industrial Range -40°C to +85°C.

General Purpose EEPROM

• The TE0716 module has also a 512Kb Serial EEPROM I2C memory (U21).
• Part number: CAT24C512WI-GT3
• Supply voltage: 1.8V (1.8V - 5.5V).
• FCLK: 100KHz/400KHz/1MHz
• Temperature: Industrial Range -40°C to +85°C.

ADCs

The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.

• Part number: NCD98011XMXTAG
• Analog supply and ADC reference voltage (VCC): 3.3V (1.65V – 3.6V).
• Digital I/O supply voltage (VDD): 3.3V (1.65V – 3.6V).
• Differential analog inputs: 1 per ADC.
• Full−Scale Analog Input Voltage Span: +VCC max V_ppd, -VCC min V_ppd, (V_CM to VCC/2).
• Absolute Voltage Range V_inp or V_inn to GND: VCC + 0.1V
• Sampling rate: 2 MSPS max.
• SNR: 70dB @1KHz fIN.
• THD: -80dB @1KHz fIN.
• Junction Temperature: Range -40°C to +125°C.

All the analog inputs are connected to B2B JP1 as follows:

All the diigital signals are connected to PL Bank 34 as follows:

Clock Sources

Ethernet

USB 2.0 ULPI transceiver

USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution with full OTG support.

• Part number: USB3320C-EZK
• Supply voltage: 1.8V and 3.3V.
• Temperature: Industrial Range -40°C to +85°C.

FTDI USB 2.0 to UART/JTAG

The TE0716 board is equipped with the FTDI FT2232H USB 2.0 to JTAG/UART adapter controller connected to the MicroUSB 2.0 B connector J13 to provide JTAG and UART access to the attached module.

There is also a 4Kbit configuration EEPROM U40 (M93C66) wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.

Do not access the FT2232H EEPROM using FTDI programming tools. By doing it, you could erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI chip is configured as JTAG interface connected to the BANK 0 Zynq SoC.

Channel B can be used as UART interface routed to the 2-Bit Bus Switch, which routes to the BANK 500 Zynq SoC, when the Output of the Bus Switch is Enable, and is available for other user-specific purposes.

LEDs

Switches

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.0 A (TBD) for system startup is recommended.

Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power-On Sequence

Voltage Monitor Circuit

Power Rails

Bank Voltages

Board to Board Connectors

TE0716 module use two 61083 BergStak® 0.8mm Plug Connectors on the bottom side.

• • Part Number: 61083-121402LF (compatible with 61082 Receptacle).
  • Operating Temperature: -40°C to +125°C.
  • Current Rating: 0.8A per Contact.
  • Number of Positions: 120 (60x per row)
  • Number of Rows: 2

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 45 mm × 65 mm.  Please download the assembly diagram for exact numbers.

• Mating height with 61982 receptacle connectors: 5mm, 7mm, 13mm and 17mm stack heights.

• PCB thickness: 1.65 mm.

Currently Offered Variants 

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Disclaimer