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Template Revision 1.9.1 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

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Overview

Firmware for PCB CPLD with designator U39. Second CPLD Device in Chain: LCMX02-1200HC

Feature Summary

Power Management
...

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD Name	Direction	Pin	Pullup/Down	Bank Power	Description
BOOT_R / BOOTMODE_R	out	N12	NONE	3.3V
BOOT_R5 / BOOTMODE_R5	out	M11	DOWN	3.3V
CLK_125MHz	in	G13	NONE	1.8V
EN_3V3	out	A2	DOWN	3.3V
EN1	in	A9	UP	3.3V
ETH-CLK-EN / EN_ETH_CLK	out	J14	NONE	1.8V
ETH-MDC / mdc	in	L14	UP	1.8V
ETH-MDIO / mdio	inout	K14	UP	1.8V
ETH-RST	out	E14	DOWN	1.8V
INIT	in	C9	UP	3.3V
INT1 / INT2	in	P4	UP	3.3V
INT2 / INT1	in	P6	UP	3.3V
JTAGMODE	in	B9		3.3V
LED1	out	P2	NONE	3.3V
LED2	out	N3	DOWN	3.3V
MEM-MAC / MAC_IO	inout	M14	UP	1.8V
MEM-SHA / SHA_IO	inout	N14	UP	1.8V
MIO14	inout	M4	NONE	3.3V
MIO15	inout	N4	NONE	3.3V
MIO7	in	P11	UP	3.3V
MMC_RST	out	G14	DOWN	1.8V
MODE / BOOTMODE_IN	in	C8	UP	3.3V
MODE / BOOTMODE_IN2	in	M9	UP	3.3V
MR / POR_B	out	P12	UP	3.3V
NetU19_B12		B12			/ currently_not_used
NetU19_B13		B13			/ currently_not_used
NetU19_B2		B2			/ currently_not_used
NetU19_B3		B3			/ currently_not_used
NetU19_B7		B7			/ currently_not_used
NetU19_C1		C1			/ currently_not_used
NetU19_C10		C10			/ currently_not_used
NetU19_C12 / Dummy	out	C12	DOWN	3.3V
NetU19_C3		C3			/ currently_not_used
NetU19_C6 / RST	in	C6	UP	3.3V
NetU19_C7		C7			/ currently_not_used
NetU19_E1		E1			/ currently_not_used
NetU19_E12		E12			/ currently_not_used
NetU19_F13		F13			/ currently_not_used
NetU19_F3		F3			/ currently_not_used
NetU19_G3		G3			/ currently_not_used
NetU19_H3		H3			/ currently_not_used
NetU19_J3		J3			/ currently_not_used
NetU19_K13		K13			/ currently_not_used
NetU19_K3		K3			/ currently_not_used
NetU19_L3		L3			/ currently_not_used
NetU19_M12		M12			/ currently_not_used
NetU19_M2		M2			/ currently_not_used
NetU19_M3		M3			/ currently_not_used
NetU19_N13		N13			/ currently_not_used
NetU19_N5		N5			/ currently_not_used
NetU19_N7		N7			/ currently_not_used
NetU19_N8		N8			/ currently_not_used
NOSEQ	inout	A3	DOWN	3.3V
ON_1V0	out	A12	NONE	3.3V
ON_1V5	out	M7	NONE	3.3V
ON_1V8	out	A11	NONE	3.3V
OTG-RST	out	B14	DOWN	1.8V
PG_1V0	in	A7	UP	3.3V
PG_1V5	in	N6	UP	3.3V
PG_1V8	in	A10	UP	3.3V
PG_3V3 / POR	in	C11	UP	3.3V
PGOOD	inout	B8	UP	3.3V
PHY_CONFIG	inout	C14	DOWN	1.8V
PHY_LED0	inout	F14	NONE	1.8V
PHY_LED1	inout	D12	NONE	1.8V
PHY_LED2	inout	C13	NONE	1.8V
PJTAG_R	out	N10	NONE	3.3V
PROG_B	in	A13	UP	3.3V
PS-RST / SRST_B	out	M13	UP	1.8V
PUDC_B	inout	E3	DOWN	VCCIO34
RESIN	in	C4	UP	3.3V
RST / RST_SENSE	in	P3	NONE	3.3V
RTC_INT	in	N2	UP	3.3V
SCL	inout	P8	UP	3.3V
SDA	inout	P7	UP	3.3V
SPK_L		M5			/ currently_not_used
SPK_R		M8			/ currently_not_used
TCK / C_TCK	out	P13	DOWN	3.3V
TDI / C_TDI	out	P9	DOWN	3.3V
TDO / C_TDO	in	M10	DOWN	3.3V
TMS / C_TMS	out	N9	DOWN	3.3V
VCCIO34		E2			/ currently_not_used
VCCIO34		F2			/ currently_not_used
VCCIO34		H2			/ currently_not_used
VCCIO34		J2			/ currently_not_used
VCCIO34		K2			/ currently_not_used
X_TCK / M_TCK	in	B6	DOWN	3.3V
X_TDI / M_TDI	in	B4	DOWN	3.3V
X_TDO / M_TDO	out	A4	DOWN	3.3V
X_TMS / M_TMS	in	A6	DOWN	3.3V
X1	in	F1	UP	VCCIO34
X2 / XIO4	inout	C2	UP	VCCIO34
X3 / XIO5	inout	B1	UP	VCCIO34
X4 / XIO6	inout	D1	UP	VCCIO34
X5	out	J1	NONE	VCCIO34
X6		H1			/ currently_not_used
X7	in	M1	UP	VCCIO34
XCLK	out	K1	NONE	VCCIO34
? / SIG1	in	E13	NONE	1.8V	This port exists in VHDL code but this pin is connected with 1.8V in the schematic REV03 ????

Functional Description

JTAG

Power

...

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

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Date	Document Revision	Description
		Work in progress
2017-06-07	v.19	Initial release
	All

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