Template Revision 1.9.1 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>


Table of contents

Overview

Firmware for PCB CPLD with designator U39. Second CPLD Device in Chain: LCMX02-1200HC

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
BOOT_R / BOOTMODE_RoutN12NONE3.3VIf low then the QSPI flash can not be written. (Write protect)
BOOT_R5 / BOOTMODE_R5outM11DOWN3.3VIf low then the QSPI flash will be reset. (HOLD/RESET)
CLK_125MHzinG13NONE1.8V125MHZ Clock Output of Ethernet transceiver chip (88E1512-A0-NNP2C000) that synchronized with the 25MHZ reference clock
EN_3V3outA2DOWN3.3VIf high then the 3.3V power will be switched ON.
EN1inA9UP3.3VUser Enable. Enables the DC-DC converters and on board supplies (Active High). (B2B JM1-28)(DIP Switch on the carrier board) . Not used if NOSEQ = '1'
ETH-CLK-EN / EN_ETH_CLKoutJ14NONE1.8VEnable pin for U9 oscillator chip U9 (SiT8008BI-73-18S-25.000000E) to feed a clock to Ethernet Transceiver(U8). Enabled as default.
ETH-MDC / mdcinL14UP1.8VManagement Data Clock reference for the Ethernet transceiver chip. This pin is connected with MIO52 of FPGA too and can be activated in Zynq7 adjustment.
ETH-MDIO / mdioinoutK14UP1.8VIt is Management Data pin of Ethernet transceiver chip to transfer in and out of the device synchronously to mdc. It is connected with MIO53 of FPGA.
ETH-RSToutE14DOWN1.8VReset pin of Ethernet transceiver chip. (Active low)
INITinC9UP3.3VINIT_B_0 pin of FPGA. (Active low). This pin must be tristate for PL configuratuion. By user or device held low until is ready to be configured.
INT1 / INT2inP4UP3.3VMEMS Interrupt 1 of 3D accelerometer and 3D magnetometer chip U22 (LSM303DTR) (Active High)
INT2 / INT1inP6UP3.3VMEMS Interrupt 2 of 3D accelerometer and 3D magnetometer chip U22 (LSM303DTR) (Active High)
JTAGMODEinB9
3.3VEnable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
LED1outP2NONE3.3VDisplay green LED (D2)
LED2outN3DOWN3.3VDisplay red LED (D5)
MEM-MAC / MAC_IOinoutM14UP1.8VSerial Clock/Data input/Output of Serial EEPROM (11AA02E48T-I/TT) U17
MEM-SHA / SHA_IOinoutN14UP1.8VSDA for CryptoAuthentication Chip (ATSHA204A-STUCZ-T) U10
MIO14inoutM4NONE3.3VRX pin of UART0
MIO15inoutN4NONE3.3VTX pin of UART0
MIO7inP11UP3.3VThis pin is used as GPIO.
MMC_RSToutG14DOWN1.8VReset pin of eMMC memory (MTFC16GJVEC-2M WT) U15
MODE / BOOTMODE_INinC8UP3.3VLatched as BOOTMODE once at power-up, can be used later as I/O, weak pull up. Force low for boot from the SD Card. Latched at power on only, not on soft reset (B2B-JM1 pin 32) 
MODE / BOOTMODE_IN2inM9UP3.3VLatched as BOOTMODE once at power-up, can be used later as I/O, weak pull up. Force low for boot from the SD Card. Latched at power on only, not on soft reset (B2B-JM1 pin 32) 
MR     / POR_BoutP12UP3.3VPower-on-reset pin. This pin is connected with supply voltage monitor chip (TPS3106K33DBVR) U26 and controls the PS_POR_B pin of FPGA. (Active Low)
NetU19_B12
B12

/ currently_not_used
NetU19_B13
B13

/ currently_not_used
NetU19_B2
B2

/ currently_not_used
NetU19_B3
B3

/ currently_not_used
NetU19_B7
B7

/ currently_not_used
NetU19_C1
C1

/ currently_not_used
NetU19_C10
C10

/ currently_not_used
NetU19_C12 / DummyoutC12DOWN3.3V
NetU19_C3
C3

/ currently_not_used
NetU19_C6 / RSTinC6UP3.3V
NetU19_C7
C7

/ currently_not_used
NetU19_E1
E1

/ currently_not_used
NetU19_E12
E12

/ currently_not_used
NetU19_F13
F13

/ currently_not_used
NetU19_F3
F3

/ currently_not_used
NetU19_G3
G3

/ currently_not_used
NetU19_H3
H3

/ currently_not_used
NetU19_J3
J3

/ currently_not_used
NetU19_K13
K13

/ currently_not_used
NetU19_K3
K3

/ currently_not_used
NetU19_L3
L3

/ currently_not_used
NetU19_M12
M12

/ currently_not_used
NetU19_M2
M2

/ currently_not_used
NetU19_M3
M3

/ currently_not_used
NetU19_N13
N13

/ currently_not_used
NetU19_N5
N5

/ currently_not_used
NetU19_N7
N7

/ currently_not_used
NetU19_N8
N8

/ currently_not_used
NOSEQinoutA3DOWN3.3VUsage CPLD Variant depends. (B2B-NOSEQ pin 7) Forces the 1.0V and 1.8V DC-DC converters always ON when high. Can be used as an I/O after boot.
ON_1V0outA12NONE3.3VEnable pin for 1.0 V DC-DC (Active High)
ON_1V5outM7NONE3.3VEnable pin for 1.5 V DC-DC (Active High)
ON_1V8outA11NONE3.3VEnable pin for 1.8 V DC-DC (Active High)
OTG-RSToutB14DOWN1.8VReset pin for high speed USB transceiver (USB3320C-EZK) U18 (Active Low)
PG_1V0inA7UP3.3VPower OK (POK) pin of 1.0V DC-DC converter EN6347QI (U1). If High then the output voltage of regulator is within 10% of nominal value (OK).
PG_1V5inN6UP3.3VPower OK (POK) pin of 1.5V DC-DC converter EP53F8QI (U2). If High then the output voltage of regulator is Ok.
PG_1V8inA10UP3.3VPower OK (POK) pin of 1.8V DC-DC converter EP53F8QI (U3). If High then the output voltage of regulator is Ok.
PG_3V3 / PORinC11UP3.3VPOR Reset pin. This pin is connected with PG_3V3. As long as the VCCIO34 voltage is zero, this pin will remain low.
PGOODinoutB8UP3.3VPower good output as default, can be used as I/O. (B2B JM1-Pin 30) Forced low until all on-board power supplies are working properly.
PHY_CONFIGinoutC14DOWN1.8VHardware configuration pin of Ethernet transceiver (88E1512-A0-NNP2C000).
PHY_LED0inoutF14NONE1.8VLED output 0 of Ehternet transceiver chip
PHY_LED1inoutD12NONE1.8VLED output 1 of Ehternet transceiver chip
PHY_LED2inoutC13NONE1.8VLED output 2 or interrupt output pin (Active Low) of Ehternet transceiver chip
PJTAG_RoutN10NONE3.3VThis pin in the schematic is connected with SPI-DQ0/M0 Pin
PROG_BinA13UP3.3V

By pulsing this pin any configuration that is currently loaded is cleared and the PL prepared to load new configuration. (Active Low)

PS-RST / SRST_BoutM13UP1.8VPS software reset  (Active Low)
PUDC_BinoutE3DOWNVCCIO34

Selects the enable or disable of pull-ups during configuration on the user I/O pins. (Active Low)  Enables internal pull-up resistors on the

select I/O pins after power-up and during configuration.

RESINinC4UP3.3VMaster reset input (Active Low). Default mapping forces POR_B reset to Zynq PS
RST / RST_SENSEinP3NONE3.3VReset pin that is connected with PS_PORT_B (Power-on-reset) (Active Low)
RTC_INTinN2UP3.3VInterrupt output or frequency output of RTC chip (ISL12020MIRZ) U20 (Active Low)
SCLinoutP8UP3.3VI2C clock pin of MEMS chip (LSM303DTR) U22
SDAinoutP7UP3.3VI2C data pin of MEMS chip (LSM303DTR) U22
SPK_L
M5

/ currently_not_used
SPK_R
M8

/ currently_not_used
TCK / C_TCKoutP13DOWN3.3VZynq JTAG clock pin
TDI / C_TDIoutP9DOWN3.3VZynq JTAG data input pin
TDO / C_TDOinM10DOWN3.3VZynq JTAG data output pin
TMS / C_TMSoutN9DOWN3.3VZynq JTAG mode select pin
VCCIO34
E2

/ currently_not_used
VCCIO34
F2

/ currently_not_used
VCCIO34
H2

/ currently_not_used
VCCIO34
J2

/ currently_not_used
VCCIO34
K2

/ currently_not_used
X_TCK / M_TCKinB6DOWN3.3VFTDI JTAG clock pin (B2B-JM1-pin 99)
X_TDI / M_TDIinB4DOWN3.3VFTDI JTAG data input pin (B2B-JM1-pin 95)
X_TDO / M_TDOoutA4DOWN3.3VFTDI JTAG data output pin (B2B-JM1-pin 97)
X_TMS / M_TMSinA6DOWN3.3VFTDI JTAG mode select pin (B2B-JM1-pin 93)
X1inF1UPVCCIO34CPLD pin to the FPGA (L16). I2C clock from FPGA
X2 / XIO4inoutC2UP

VCCIO34

CPLD pin to the FPGA (M15). ETH PHY LED0
X3 / XIO5inoutB1UPVCCIO34CPLD pin to the FPGA (N15). ETH PHY LED1
X4 / XIO6inoutD1UPVCCIO34CPLD pin to the FPGA (P16). ETH PHY LED2
X5outJ1NONEVCCIO34CPLD pin to the FPGA (P22). I2C data to FPGA
X6
H1

/ currently_not_used
X7inM1UPVCCIO34CPLD pin to the FPGA (N22). I2C data from FPGA
XCLKoutK1NONEVCCIO34CPLD pin to the FPGA (K19). ETH PHY clock to FPGA
- / SIG1inE13NONE1.8VThis pin is connected with VCCIO34 directly in the schematic REV03 and has no lable in the schematic.


SC registers

Value (CR1[3:0])LED1 (Green)Value (CR1[7:4])LED2 (Red)Value (CR1[11:8])NOSEQDescription
0001

PHY_LED0

0001PHY_LED00001PHY_LED0
0010

PHY_LED1

0010PHY_LED10010PHY_LED1
0011

PHY_LED2

0011PHY_LED20011PHY_LED2
0100

MIO7

0100MIO70100MIO7
0101

RTC_INT

0101RTC_INT0101RTC_INT
0110

OFF

0110OFF0110OFF
0111

ON

0111ON0111ON
1000XIO41000XIO51000XIO6
1001Not MIO141001Not MIO151001uio_unidir
1010Not MIO14/Not MIO151010Not MIO14/Not MIO151010

DefaultMIO7DefaultmodeblinkDefaultPHY_LED0


CR1Description
15:12-
11:8NOSEQ Mux
7:4LED1 Mux
3:0LED2 Mux


Value (CR2[3:0])XIO4Value (CR2[7:4])XIO5Value (CR2[11:8])XIO6Value (CR2[15:12])XCLKDescription
0001

MIO7

0001

MIO14_in

0001

MIO15_in

0001RTC_INT
0010

SHA_IO_in

0010-0010-0010osc_clk
0011MAC_IO_in0011RTC_INT0011osc_clk0011-
1000uio_unidir1000uio_unidir1000uio_unidir1000-
0110'Z'0110'Z'0110'Z'0110-
0111---0111INTR0111-
DefaultPHY_LED0DefaultPHY_LED1DefaultPHY_LED2DefaultCLK_125MHZ


CR2Description
15:12XCLK Mux
11:8XIO6 Mux
7:4XIO5 Mux
3:0XIO4 Mux


SR1Description
0

INT1

1INT2
2RTC_INT
3PHY_LED2
7BOOTMODE_LATCHED
8BOOTMODE_IN2
9BOOTMODE_IN
10NOSEQ
11NOSEQ_LATCHED
12WD_EVENT
13PG_1V5
14EXTRA_ENABLED or WDOG_ENABLED
15mac_valid


GPIO_inputDescription
0

PHY_LED0

1PHY_LED1
2MIO7
3NOSEQ
4RESIN_g
5EN1_g
6BOOTMODE_LATCHED
7BOOTMODE_IN
8INT1
9INT2
10RTC_INT
11PHY_LED2
12'0'
13'0'


AddrR/WRegister nameDescripion
0RO

1RO

2ROID1Identifier Register 1
3ROID2Identifier Register 2
4ROID3Identifier Register 3
5RWCR1Control Register 1: LED's
6RWCR2Control Register 2; XIO Control
7RWCR3Control Register 3; Reset, Interrupt
8ROSR1Status Register
9ROMAChiHighest bytes of primary MAC Address
0xAROMACmiMiddle bytes of primary MAC Address
0xBROMACloLowest bytes of primary MAC Address
0xCCR4
reserved do not use
0xDRWMMD_CRMMD Control Register
0xERWMMD_ADMMD Address/Data
0xF-
reserved do no use
other-
reserved do not use


Value (uio_sm_cnt[8:5])uio_io_dataDescription
0000

MIO7


0001RTC_INT
0010INT1
0100INT2
0011PHY_LED0
0100PHY_LED1
0101PHY_LED2
0110BOOTMODE_IN
0111MIO14_in
1000MIO15_in
1001XIO4_in
1010XIO5_in
1011XIO6_in
1100WD_HIT
1101'0'
1110'0'


Value (uio_sm_cnt[2:1])uio_unidirDescription
01'0'
10

uio_io_data / uio_id_data


If uio_sm_cnt(4) Lown --→  uio_id_data


Functional Description

JTAG

Power

...

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription




Work in progress
2017-06-07

v.19




Initial release

All


Legal Notices