Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator




Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):


        Create DrawIO object here: Attention if you copy from other page, use


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

      • ExampleComment
        12



  • ...

Overview



Notes :

Zynq PS Design with Linux Example and Camera Demo.

Refer to http://trenz.org/te0727-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • Add basic key futures, which can be tested with the design


  • Vitis/Vivado 2020.2

  • RPI Camera 1.3 or 2.1

  • HDMI

  • PetaLinux

  • SD

  • USB

  • I2C

  • Special FSBL for QSPI programming

Revision History

Notes :

  • add every update file on the download

  • add design changes on description


Date

Vivado

Project Built

Authors

Description

2021-10-062020.2TE0727-zbzerodemo1_noprebuilt-vivado_2020.2-build_8_20211006122605.zip
TE0727-zbzerodemo1-vivado_2020.2-build_8_20211006122624.zip
Manuela Strücker
  • 2020.2 release
  • update document style
  • 0001-QSPI-s25fl127_8-2020_2.patch for restart

2020-11-24

2019.2

TE0727-zbzerodemo1_noprebuilt-vivado_2019.2-build_15_20201124064113.zip
TE0727-zbzerodemo1-vivado_2019.2-build_15_20201124064045.zip

Oleksandr Kiyenko/ John Hartfiel

  • initial release


Release Notes and Know Issues

Notes :

  • add known Design issues and general notes for the current revision

  • do not delete known issue, add fixed version time stamp if  issue fixed


Issues

Description

Workaround

To be fixed version

FSBL/ Kernel
Vivado 2020.2
Petalinux does not restart after first bootinguse 0001-QSPI-s25fl127_8-2020_2.patch from
test_board\os\petalinux\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\
---
Error message during boot "memory reservation failed"During boot message "ERROR: reserving fdt memory region failed (addr=1fc00000 size=400000)" occures.

No workaround
Camera is working, picture can be captured with fbgrab function

---

init.sh

automatically camera selection failed

select camera manually on init.sh

---


Requirements

Software

Notes :

  • list of software which was used to generate the design


Software

Version

Note

Vitis

2020.2

needed, Vivado is included into Vitis installation

PetaLinux

2020.2

needed


Hardware

Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *
Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on  "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0727-02-41C34*10_512MBREV02512MB16MBNANANA

*used as reference


Design supports following carriers:

Carrier Model

Notes

---



Additional HW Requirements:

Additional Hardware

Notes

USB Power

Use USB2.0 or higher for power supply via USB

USB Cable

Connect to USB2 or better USB3 Hub for proper power supply over USB

Raspberry Pi Camera Rev 1.3 or Camera Rev 2.1

--

Monitor

DELL Model Number: U2412M*

HDMI Cable

--

HDMI to Mini HDMI adapter

--

*used as reference

Content

Notes :

  • the content of the zip file

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration



Additional Sources

TypeLocationNotes
init.sh<project folder>\misc\sd\Additional Initialization Script for Linux (used to enable camera)



Prebuilt

Notes :

  • prebuilt files
  • Template Table:

    • File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Source*.scr

      Distro Boot file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Source*.scr

Distro Boot file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems



Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow



Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"

  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note: Select correct one, see also Vivado Board Part Flow


  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    TE::hw_build_design -export_prebuilt


    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ZynqMP

      • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ...

      • ...


  8. Generate Programming Files with Vitis

    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


Launch



Note:

  • Programming and Startup procedure

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

Boot.bin on QSPI Flash and image.ub and boot.scr on SD.

  1. Connect USB Power In to get power on module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"


  3. TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0727 (optional)


    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup


  4. Remove cable from USB Power In
  5. Copy image.ub and boot.scr on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    • Important: Do not copy Boot.bin on SD (it is not used; see SD note), only other files.
  6. Copy init.sh on SD
    • location: <project folder>/misc/sd/
  7. Insert SD-Card in SD-Slot.
  8. Connect USB Power In to get power on module

SD-Boot mode

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot (fsbl, u-boot) and SD for secondary boot (image.ub, boot.src)


JTAG

Not used on this Example.

Usage

  1. Prepare HW like described in section Programming

  2. Connect UART USB (most cases same as JTAG)

  3. Insert SD Card with image.ub and boot.src

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr


  4. Power On PCB

    1. Zynq Boot ROM loads FSBL from QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for ZynqMP???

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for Microblaze

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze,

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


    for native FPGA

    ...


Linux

  1. Open Serial Console (e.g. putty)

    1. Speed: 115200

    2. select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


  2. Linux Console:

    petalinux login: root
    Password: root


    Note: Wait until Linux boot finished


  3. You can use Linux shell now.

    i2cdetect -y -r 1 (check I2C (Bus 0...2 possible)) 
    lsusb             (USB check)


  4. Camera stream will be enabled via init.sh script on SD

  5. Take image from camera (must be enabled with init.sh script):

    fbgrab -d /dev/fb0 /run/media/sda1/camera.png (write image to USB Stick)
    


System Design - Vivado



Note:

  • Description of Block Design, Constraints... BD Pictures from Export...

Block Design

PS Interfaces

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

Type

Note

DDR

---

QSPI

MIO

SD0---

SD1

MIO

I2C0

EMIO

I2C1

MIO

UART1

MIO

GPIO MIO

MIO

SWDTEMIO

TTC0..1

EMIO

WDT

MIO

USB0

MIO

USB PHY RST

MIO


Constraints

Basic module constraints

#
# Common BITGEN related settings for TE0727 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Design specific constraint

#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]


set_property PACKAGE_PIN G11 [get_ports {CEC_A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CEC_A[0]}]
set_property PACKAGE_PIN H13 [get_ports {HPD_A}]
set_property IOSTANDARD LVCMOS33 [get_ports {HPD_A}]
set_property PACKAGE_PIN G14 [get_ports {GLED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GLED[0]}]
set_property PACKAGE_PIN G12 [get_ports {IIC_A_scl_io}]
set_property PACKAGE_PIN H12 [get_ports {IIC_A_sda_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {IIC_A_*}]
set_property PACKAGE_PIN K12 [get_ports {CT_HPD[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CT_HPD[0]}]

set_property PACKAGE_PIN F12 [get_ports {HDMI_TXC_P}]
set_property PACKAGE_PIN E13 [get_ports {HDMI_TXC_N}]
set_property PACKAGE_PIN E11 [get_ports {HDMI_TX_P[0]}]
set_property PACKAGE_PIN E12 [get_ports {HDMI_TX_N[0]}]
set_property PACKAGE_PIN G15 [get_ports {HDMI_TX_P[1]}]
set_property PACKAGE_PIN F15 [get_ports {HDMI_TX_N[1]}]
set_property PACKAGE_PIN F14 [get_ports {HDMI_TX_N[2]}]
set_property PACKAGE_PIN F13 [get_ports {HDMI_TX_P[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {HDMI_*}]

set_property PACKAGE_PIN J11 [get_ports {GPIO_tri_io[0]}]
set_property PACKAGE_PIN H11 [get_ports {GPIO_tri_io[1]}]
set_property PACKAGE_PIN J15 [get_ports {GPIO_tri_io[2]}]
set_property PACKAGE_PIN L15 [get_ports {GPIO_tri_io[3]}]
set_property PACKAGE_PIN N13 [get_ports {GPIO_tri_io[4]}]
set_property PACKAGE_PIN P8  [get_ports {GPIO_tri_io[5]}]
set_property PACKAGE_PIN M10 [get_ports {GPIO_tri_io[6]}]
set_property PACKAGE_PIN L12 [get_ports {GPIO_tri_io[7]}]
set_property PACKAGE_PIN M11 [get_ports {GPIO_tri_io[8]}]
set_property PACKAGE_PIN P10 [get_ports {GPIO_tri_io[9]}]
set_property PACKAGE_PIN P9  [get_ports {GPIO_tri_io[10]}]
set_property PACKAGE_PIN K15 [get_ports {GPIO_tri_io[11]}]
set_property PACKAGE_PIN M9  [get_ports {GPIO_tri_io[12]}]
set_property PACKAGE_PIN L13 [get_ports {GPIO_tri_io[13]}]
set_property PACKAGE_PIN L14 [get_ports {GPIO_tri_io[14]}]
set_property PACKAGE_PIN M15 [get_ports {GPIO_tri_io[15]}]
set_property PACKAGE_PIN J14 [get_ports {GPIO_tri_io[16]}]
set_property PACKAGE_PIN N14 [get_ports {GPIO_tri_io[17]}]
set_property PACKAGE_PIN K11 [get_ports {GPIO_tri_io[18]}]
set_property PACKAGE_PIN N9  [get_ports {GPIO_tri_io[19]}]
set_property PACKAGE_PIN J13 [get_ports {GPIO_tri_io[20]}]
set_property PACKAGE_PIN H14 [get_ports {GPIO_tri_io[21]}]
set_property PACKAGE_PIN R10 [get_ports {GPIO_tri_io[22]}]
set_property PACKAGE_PIN M14 [get_ports {GPIO_tri_io[23]}]
set_property PACKAGE_PIN P15 [get_ports {GPIO_tri_io[24]}]
set_property PACKAGE_PIN M12 [get_ports {GPIO_tri_io[25]}]
set_property PACKAGE_PIN K13 [get_ports {GPIO_tri_io[26]}]
set_property PACKAGE_PIN R15 [get_ports {GPIO_tri_io[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_io*}]

set_property PACKAGE_PIN N12 [get_ports {CSI_C_N}]
set_property PACKAGE_PIN N11 [get_ports {CSI_C_P}]
set_property PACKAGE_PIN R8  [get_ports {CSI_D_N[0]}]
set_property PACKAGE_PIN R7  [get_ports {CSI_D_P[0]}]
set_property PACKAGE_PIN R13 [get_ports {CSI_D_N[1]}]
set_property PACKAGE_PIN R12 [get_ports {CSI_D_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_*}]
set_property PACKAGE_PIN N8  [get_ports {CLP_D_N[0]}]
set_property PACKAGE_PIN N7  [get_ports {CLP_D_P[0]}]
set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}]
set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}]
#set_property PACKAGE_PIN R11 [get_ports {CLP_C_N}]
#set_property PACKAGE_PIN P11 [get_ports {CLP_C_P}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_*}]
set_property PULLDOWN true [get_ports {CLP_*}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
create_clock -period 6.250 -name csi_clk -add [get_ports CSI_C_P]


set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_N[1]}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_N[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_P[1]}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_P[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_D_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_D_P[0]}]

set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}]
set_property PACKAGE_PIN N8 [get_ports {CLP_D_N[0]}]
set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}]
set_property PACKAGE_PIN N7 [get_ports {CLP_D_P[0]}]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

Software Design - Vitis



Note:

  • optional chapter separate

  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2020.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2020.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • Enable VDM controller

fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0727

Hello TE0727 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.


Software Design -  PetaLinux



Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • No changes

U-Boot

Start with petalinux-config -c u-boot
Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

#include <configs/zynq-common.h>
#include <configs/platform-auto.h>

Device Tree

/include/ "system-conf.dtsi"
/ {
};
  
  
/ {
    #address-cells = <1>;
    #size-cells = <1>;
   
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        // HDMI Output frame buffer
        hdmi_fb_reserved_region@1FC00000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1FC00000 0x400000>;
            // 128M (R modules)
            //reg = <0x7C00000 0x400000>;
        };
/*  // Use second frame buffer if you want separate area for camera image  
        camera_fb_reserved_region@1FC00000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1FC00000 0x400000>;
            // 128M (R modules)
            //reg = <0x7800000 0x400000>;
        };
*/ 
    };
   
    hdmi_fb: framebuffer@0x1FC00000 {           // HDMI out
        compatible = "simple-framebuffer";
        // 512M (M modules)
        reg = <0x1FC00000 (1280 * 720 * 4)>;    // 720p
        // 128M (R modules)
        //reg = <0x7C00000 (1280 * 720 * 4)>;   // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
        status = "okay";
    };
/*  // In "go through" mode only one framebuffer is used
    camera_fb: framebuffer@0x1FC00000 {         // CAMERA in
        compatible = "simple-framebuffer";
        // 512M (M modules)
        reg = <0x1FC00000 (1280 * 720 * 4)>;    // 720p
        // 128M (R modules)
        //reg = <0x7800000 (1280 * 720 * 4)>;   // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
    };
*/ 
    vcc_3V3: fixedregulator@0 {
        compatible = "regulator-fixed";
        regulator-name = "vccaux-supply";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        regulator-always-on;
    };
};
  
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
  
/*
* We need to disable Linux VDMA driver as VDMA
* already configured in FSBL
*/


&video_out_axi_vdma_0 {
	// Solution 1: Disable standard VDMA driver (VDMA configuration should be done in the FSBL)
	status = "disabled";	
	// Solution 2: Configure VDMA using the custom driver (VDMA configuration in FSBL should be disabled)
    //compatible = "trenz,vdmafb";
    //width = <1280>;
    //height = <720>;
    //stride = <(1280 * 4)>;
    //format = "a8b8g8r8";
};

&video_in_axi_vdma_0 {
	// Solution 1: Disable satandard VDMA driver (VDMA configuration should be done in the FSBL)
	status = "disabled";
};

&gpio0 {
    interrupt-controller;
    #interrupt-cells = <2>;
};
  

/* I2C1 - for REV02 */ 
&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;

	i2cmux: i2cmux@70  {
		compatible = "nxp,pca9540";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		ID_I2C@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		CSI_I2C@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
	};
};



/* USB */  
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
  
&usb0 {
    usb-phy = <&usb_phy0>;
} ;

FSBL patch

Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_FB_SIMPLE=y

  • # CONFIG_FRAMEBUFFER_CONSOLE is not set


Change linux-xlnx_%.bbappend:

FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"

SRC_URI += "file://devtool-fragment.cfg \
            file://0001-QSPI-s25fl127_8-2020_2.patch \
            "
  • Add 0001-QSPI-s25fl127_8-2020_2.patch to "<project folder>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\"

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y

  • CONFIG_i2cpick=y
  • CONFIG_util-linux-mount=y
  • CONFIG_util-linux-umount=y

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

rpicam

Application used to enable and configure Raspbery Pi camera module

fbgrab

Application used to take screenshot from camera



Additional Software



Note:

  • Add description for other Software, for example SI CLK Builder ...

  • SI5338 and SI5345 also Link to:

No additional software is needed.

Appx. A: Change History and Legal Notices


Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

  • Note this list must be only updated, if the document is online on public doc!

  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Date

Document Revision

Authors

Description

  • Docu correction FSBL

2021-10-26v.9Manuela Strücker
  • 2020.2 release
2020-11-24v.5John Hartfiel
  • 2019.2 release

--

all

--


Legal Notices




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