Template Revision 1.0 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
Important General Note:
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This demo is a Webserver which utilizes SmartFusion2 SoC ARM Cortex-M3, Ethernet, USB / COM-port, Real Time Clock and the on-board LEDs.
The demo is offered in two variants, one which is stored into the embedded non-volatile memory (eNVM) and the seconde one which stored to the external DDR3/L SDRAM memory and therefore volatile.
Refer to http://trenz.org/tem0002-info for the current online version of this manual and other available documentation.
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Design supports following modules:
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Additional hardware Requirements:
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Content of the zip archive "TEM0002-SmartBerry_Ref.Des.-HelloWorld_Demo-Webserver_Libero-X.y_Datum-Time":
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The Trenz Electronic Reference Designs and Demos are usable with the specified Microsemi Libero / SoftConsole version. Usage of a different Microsemi Libero / SoftConsole software versions is not recommended.
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Reference Designs / Demos are available via the following link:
The download is a ZIP compressed archive. Extract the archive before usage.
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The Hardware and Software Reference / Demo -Designs Projects are available as a prebuild zip archive. The archive contains a Libero Hardware Project and a SoftConsole Workspace folder, they were created and tested in windows environment.
This SoftConsole Workspace contains the Software Project Hello World and the Demo Webserver, the demo is offered in two variants. The board configuration file "microsemi-smartfusion2-smartberry-ddr.cfg" is required for the usage of the Software projects via the IDE SoftConsole.
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Executing a Reference / Demo Design on a module requires the powering of it and a JTAG or UART Connection for Programming and Communication. Often the programming is a two fold process, where the first programming configures the FPGA and the second programming flashes Software code to be executed inside the FPGA / ARM processor.
Connect the modules micro USB connector to your host pc, this enables the powering of the module and a simultaneous JTAG and UART connection .
Only necessary for running the Demo Webserver:
The demo is configured to establish a network connection via the DHCP protocol, therefore, if a a free router port is used, no further port setup is required.
If a "direct Ethernet Connection" between Host PC and module is used, the user must know how to setup this connection type. Further down in this chapter is explained how to setup the Demo Webserver and recompile it, so that it uses a static IP.
When the module is connected via USB cable to your demo host computer, in the Windows Device Manager appear the following tree board driver related devices:
In section Ports (COM & LPT):
In section Universal Serial Bus controllers:
The Device Manager is accessible via "Right mouse click context menu" from the Windows Start Menu Button. When these devices are not visible, the driver installation through libero could be faulty.
Programming of the Hardware reference Design requires to open the FPGA Design IDE Libero
The Hardware Reference Design can be opened via "Project > Open Project" in the top right corner of Libero (picture above - upper green rectangle). A file dialogue opens, point the dialogue along the extracted download to the folder containing the Hardware Reference Design.
Disk :\ Path-to-the-Demo-archive \ Extracted ZIP-archive \ Libero-X.y_Referenz-Design\
Double left mouse click onto the project file "Referenz-Design_XY .prjx" to open it. The board is automatically selected and setup to be flashed by Libero.
In the upper left section of Libero, select the tab "Design Flow" (picture above - lover green rectangle) and flash it to the board via "Program Design > and double left mouse click onto "Run PROGRAM Action" (picture above - row with blue background).
Warnings should not affect the functionality of a Reference / Demo -Design.
Before flashing any Software Project to the module, open a comport terminal to the boards comport, so that it's messages can be captured.
Open SoftConsole and press "Browse..." near the right edge. A file dialogue opens, point the dialogue along the extracted download to the folder containing the SoftConsole Workspace.
Disk :\ Path-to-the-Demo-archive \ Extracted ZIP-archive \ Softconsole-X.y-Workspace \
Confirm your selectioin by pressing "Ok" , the dialogue closes, and open The SoftConsole by pressing "Launch"
Subsequently the program opens and shows the software project's who are contained inside the workspace to the left, under "Project Explorer".
To simply run a Project, press the triangle right to the button marked with a "R" in the picture above and select a variant of the demo.
Pressing the triangle next to the button marked with "D" let you select which variant to be executed in debug mode.
Debug controls - Resume - Pause - Stop
Switch between Debug and Run perspective (upper right corner program window)
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# Microsemi I/O Physical Design Constraints file # User I/O Constraints file # Version: v12.4 12.900.0.16 # Family: SmartFusion2 , Die: M2S010 , Package: 400 VF # Date generated: Mon Nov 16 11:11:16 2020 # # User Locked I/O Bank Settings # # # Unlocked I/O Bank Settings # The I/O Bank Settings can be locked by directly editing this file # or by making changes in the I/O Attribute Editor # # # User Locked I/O settings # set_io Eth_LED1A \ -pinname Y10 \ -fixed yes \ -DIRECTION OUTPUT set_io Eth_LED1B \ -pinname U12 \ -fixed yes \ -DIRECTION OUTPUT set_io Eth_LED2A \ -pinname V14 \ -fixed yes \ -DIRECTION OUTPUT set_io Eth_LED2B \ -pinname U14 \ -fixed yes \ -DIRECTION OUTPUT set_io GLED \ -pinname G17 \ -fixed yes \ -DIRECTION OUTPUT set_io GPIO_5_F2M_taster_S4 \ -pinname E17 \ -fixed yes \ -DIRECTION INPUT set_io GPIO_6_F2M_taster_S5 \ -pinname E16 \ -fixed yes \ -DIRECTION INPUT set_io MAC_GMII_MDC \ -pinname N1 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION OUTPUT set_io PHY_LED0 \ -pinname U11 \ -fixed yes \ -DIRECTION INPUT set_io PHY_LED1 \ -pinname T14 \ -fixed yes \ -DIRECTION INPUT set_io PHY_MDIO \ -pinname N2 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION INOUT set_io {PHY_RD[0]} \ -pinname K5 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION INPUT set_io {PHY_RD[1]} \ -pinname H1 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION INPUT set_io {PHY_RD[2]} \ -pinname H2 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION INPUT set_io {PHY_RD[3]} \ -pinname J4 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION INPUT set_io PHY_RESETN \ -pinname R13 \ -fixed yes \ -DIRECTION OUTPUT set_io PHY_RX_CTL \ -pinname K1 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION INPUT set_io {PHY_TD[0]} \ -pinname L1 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION OUTPUT set_io {PHY_TD[1]} \ -pinname M2 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION OUTPUT set_io {PHY_TD[2]} \ -pinname M1 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION OUTPUT set_io {PHY_TD[3]} \ -pinname M3 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION OUTPUT set_io PHY_TX_CTL \ -pinname K3 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION OUTPUT set_io RGB_B \ -pinname H6 \ -fixed yes \ -DIRECTION OUTPUT set_io RGB_G \ -pinname F6 \ -fixed yes \ -DIRECTION OUTPUT set_io RGB_R \ -pinname H5 \ -fixed yes \ -DIRECTION OUTPUT set_io RLED \ -pinname G16 \ -fixed yes \ -DIRECTION OUTPUT set_io RXC \ -pinname J2 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION INPUT set_io TXC \ -pinname K7 \ -fixed yes \ -iostd LVCMOS15 \ -DIRECTION OUTPUT # # Dedicated Peripheral I/O Settings # # # Unlocked I/O settings # The I/Os in this section are unplaced or placed but are not locked # the other listed attributes have been applied # # #Ports using Dedicated Pins # set_io DEVRST_N \ -pinname U17 \ -DIRECTION INPUT |
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
The demo projects "Smartberry_Webserver_X.y" and "Smartberry_Webserver_DDR_X.y" are identical variants of the demo, they only differ in their memory location:
UART output:
To disengaging the DHCP mode one has to setup up an IP and Gateway Address in the code unit "main.c" roughly at line 270. Alternativly, the demo hosts IP Address can be changed.
Furthermore the corresponding compiler flag needs to be deleted in the project setting. To do so, in the "Project Explorer" tab, right mouse click onto the project and select Properties in the appearing menu.
In the left section of the properties window select "C/C++ Build > Settings" in the right section select the tab "Tool Settings > GNU ARM Cross C Compiler > Preprocessor" under "Defined symbols (-D)" delete the compiler flag "NET_USE_DHCP" and press "Apply". Confirm the following dialogue and press "Cancel".
Lastly, the project needs to be recompiled. In the top menu of the SoftConsole select "Project > Build ALL / Build Project".
Warnings should not affect the demo. can be ignored.
Hello World example as endless loop instead of one console output. Each loop lights up each LED. The user buttons responds with a message at any time.
UART output:
To get content of older revision got to "Change History" of this page and select older document revision number.
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