Module: TRM Name always "TE Series Name" +TRM Example: "TE0745 TRM"
Carrier: TRM Name usually "TEB Series Name" +TRM Example: "TEB0745 TRM"
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:
If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template:
Create DrawIO object here: Attention if you copy from other page, objects are only linked.
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
Example
Comment
1
2
The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
type: Figure, Table
main section:
"OV" for Overview
"SIP" for Signal Interfaces and Pins,
"OBP" for On board Peripherals,
"PWR" for Power and Power-On Sequence,
"B2B" for Board to Board Connector,
"TS" for Technical Specification
"VCP" for Variants Currently in Production
"RH" for Revision History
name: custom, some fix names, see below
Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
"Figure_PWR_PD" for Power Distribution
"Figure_PWR_PS" for Power Sequence
"Figure_PWR_PM" for Power Monitoring
"Table_PWR_PR" for Power Rails
"Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
"Figure_TS_PD" for Physical_Dimensions
"Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
"Figure_RH_HRN" for Hardware_Revision_Number
"Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
The Trenz Electronic TE0745 is an industrial/commercial/extended grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32/64 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.
For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
SD
USB
ETH
FMC
...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
JTAG
UART
I2C
MGT
...
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank
Type
B2B Connector
I/O Signal Count
Voltage Level
Notes
12
HR
J1
48 Diff (24 LVS pair),
2 Single ended
VCCIO_12 pins J1-54, J1-55
Voltage range 1.2V to 3.3V
13
HR
J1
48 Diff (24 LVS pair),
2 Single ended
VCCIO_13 pins J1-112, J1-113
Voltage range 1.2V to 3.3V
33
HP
J3
48 Diff (24 LVS pair),
2 Single ended
VCCIO_33 pins J3-115, J3-120
Voltage range 1.2V to 1.8V
34
HP
J2
48 Diff (24 LVS pair),
2 Single ended
VCCIO_34 pins J2-29, J2-30
Voltage range 1.2V to 1.8V
35
HP
J2
48 Diff (24 LVS pair),
2 Single ended
VCCIO_35 pins J2-87, J2-88
Voltage range 1.2V to 1.8V
500
MIO
J2
5
1.8V
MIO0, MIO12 ... MIO15, user configurable I/O's on B2B
501
MIO
J3
12
1.8V
MIO40 ... MIO51, user configurable I/O's on B2B
System Controller I/O Pins
Pin Name
Direction
Function
B2B
Default Configuration
JTAG_EN
Input
JTAG select
J1-148
During normal operating mode the JTAG_EN pin should be in the low state for JTAG signals to be forwarded to the Zynq SoC. If JTAG_EN pin is set to high or left open the JTAG signals are forwarded to the System Controller CPLD.
Control line which sets in conjunction with signal 'BOOTMODE_1' connected to CPLD(BOOTMODE_1 default high) the boot source of the Zynq chip. See section "Configuration Signals".
PWR_PL_OK
Input
Power good
J2-135
Indicates stable state of PL supply voltage (low-active) after power-up sequence.
PWR_PS_OK
Input
Power good
J2-139
Indicates stable state of PS supply voltage (low-active) after power-up sequence.
MIO0
Input
PS MIO
J2-137
User I/O also connected to CPLD.
JTAG Interface
JTAG interface access is provided through the SoC's PS configuration bank 0, it is connected to B2B connector J1.
JTAG Signal
B2B Connector
TMS
J1- 144
TDI
J1- 142
TDO
J1- 145
TCK
J1- 143
JTAG_EN
J1- 148
I2C Interface
The I2C interface on B2B connector J2 has PS_3.3V as reference voltage and is connected to the Zynq SoC via voltage level translating (3.3V ↔ 1.8V) I2C bus repeater (U17).
Schematic
B2B
Notes
I2C_33_SCL
J2-119
3.3V reference voltage
I2C_33_SDA
J2-121
3.3V reference voltage
Following on-module I2C interface are connected to the same I2C bus:
I2C bus is accessible from SoC over following MIO:
MIO Pin
Signal Schematic Name
Notes
MIO 10
I2C_SCL
1.8V reference voltage
MIO 11
I2C_SDA
1.8V reference voltage
MGT Lanes
Lane
Bank
Type
Signal Name
B2B Pin
Note
0
112
GTX
MGT_RX0_P
MGT_RX0_N
MGT_TX0_P
MGT_TX0_N
J3-50
J3-52
J3-51
J3-53
1
112
GTX
MGT_RX1_P
MGT_RX1_N
MGT_TX1_P
MGT_TX1_N
J3-56
J3-58
J3-57
J3-59
2
112
GTX
MGT_RX2_P
MGT_RX2_N
MGT_TX2_P
MGT_TX2_N
J3-62
J3-64
J3-63
J3-65
3
112
GTX
MGT_RX3_P
MGT_RX3_N
MGT_TX3_P
MGT_TX3_N
J3-68
J3-70
J3-69
J3-71
4
111 1)
GTX
MGT_RX4_P
MGT_RX4_N
MGT_TX4_P
MGT_TX4_N
J1-23
J1-21
J1-22
J1-20
5
111 1)
GTX
MGT_RX5_P
MGT_RX5_N
MGT_TX5_P
MGT_TX5_N
J1-17
J1-15
J1-16
J1-14
6
111 1)
GTX
MGT_RX6_P
MGT_RX6_N
MGT_TX6_P
MGT_TX6_N
J1-11
J1-9
J1-10
J1-8
7
111 1)
GTX
MGT_RX7_P
MGT_RX7_N
MGT_TX7_P
MGT_TX7_N
J1-5
J1-3
J1-4
J1-2
1)Note: MGT bank 111 not available at XC7Z030 Zynq SoC.
MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
MIO Pin
Connected to
B2B
Notes
MIO12...14
SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
J2
QSPI
MIO Pin
Connected to
B2B
Notes
MIO0
CPLD and B2B J2-137
J2
Configurable, def. used for SD CD
MIO1...6
SPI_CS , SPI_DQ0... SPI_DQ3, SPI_SCK
-
QSPI Flash
MIO7
USB_RESET_N
-
10k pullup to PS_1.8V
MIO8
Used for CPLD Status
-
10k pullup to PS_1.8V
MIO9
ETH_PHY_RST_N
-
ETH PHY
MIO10....11
SCL/SDA
-
I2C
MIO12...13
-
J2
Configurable, def GPIO
MIO13...14
UART
Configurable, def. used for UART
MIO16...27
ETH_TXCK, ETH_TXD0..3, ETH_TXCTL
ETH_RXCK, ETH_RXD0..3, ETH_RXCTL
-
Ethernet Signals
MIO28...39
OTG_DATA4, OTG_DIR, OTG_STP, OTG_NXT,
OTG_DATA0...3, OTG_CLK, OTG_DATA5...7
-
USB
MIO40...45
MIO40..45
J3
Configurable, def. used for SD
MIO46...50
-
J3
GPIO
MIO51
I2C Reset
J3
Configurable, def. used for I2C Reset
MIO52
PHY_MDC
J3
ETH PHY
MIO53
PHY_MDIO
J3
ETH PHY
On-board Peripherals
Notes :
add subsection for every component which is important for design, for example:
Two 100 Mbit Ethernet Transciever PHY
USB PHY
Programmable Clock Generator
Oscillators
eMMCs
RTC
FTDI
...
DIP-Switches
Buttons
LEDs
Notes :
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection
Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory 256/512 Mbit (32/64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used. Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
MIO Pin
Schematic
Notes
MIO1
SPI-CS
MIO2
SPI-DQ0/M0
MIO3
SPI-DQ1/M1
MIO4
SPI-DQ2/M2
MIO5
SPI-DQ3/M3
MIO6
SPI-SCK/M4
DDR3 SDRAM
The TE0745 SoM has two volatile Intelligent Memory 512 MByte DDR3L-1600 SDRAM IC for storing user application code and data.
Part number: IM4G16D3FABG-125I
Supply voltage: 1.5V
Organization: 256M x 16 bits
DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1600 Mb/s.
RTC
An temperature compensated is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address mentioned in the table below. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.
Schematic
B2B
I2C Address
Designator
Notes
I2C_33_SCL
J2-119
0x6F
U24
I2C_33_SDA
J2-121
Programmable PLL Clock
There is a Silicon Labs I2C programmable quad PLL clock generator (U16) on-board. It's output frequencies can be programmed by using the I2C-bus with address 0x70.
A 25.00 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C-bus connected between the Zynq module (master) and reference clock signal generator (slave).
The System Controller CPLD (U2) is central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For current CPLD Firmware description, check TE0745 CPLD
USB ULPI PHY
Hi-speed USB ULPI PHY (U32) is provided on the board. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U33).
MAC Address EEPROM
A serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use.
EEPROM
Schematic
MIO
I2C Address
Designator
Notes
I2C_SCL
MIO10
0x53
U23
I2C_SDA
MIO11
Ethernet PHY
On-board Gigabit Ethernet PHY (U7) is provided on the board. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
Schematic
B2B
Notes
PHY_MDIO
-
Connected to MIO52
PHY_MDIO0+/ MDIO0-
J2-120/122
PHY_MDIO1+/ MDIO1-
J2-126/128
PHY_MDIO2+/ MDIO2-
J2-132/134
PHY_MDIO3+/ MDIO3-
J2-138/140
PHY_LED1
J2-144
PHY_LED2
J2-146
PHY_LED3
J2-148
PHY_CLK125M
J2-150
PHY_MDC
-
Connected to MIO53
LEDs
Schematic
Color
Connected to
Active level
Note
Note
D1
Green
System Controller CPLD (bank 3, pin 5)
High
System main status LED, blinking indicates system activity
D2
Red
Zynq chip, bank 0 (config bank), 'DONE' pin
Low
Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.
This LED remains OFF if System Controller CPLD can not power up the PL supply voltage.
Clock Sources
Designator
Schematic Name
Frequency
Note
U21
-
25.00 MHz
Quad PLL clock generator U16, pin 3
U12
PS_CLK
33.33 MHz
Bank 500 (MIO0 bank), pin B24
U33
OTG-RCLK
52.00 MHz
USB 2.0 transceiver PHY U32, pin 26
U9
ETH_CLKIN
25.00 MHz
Gigabit Ethernet PHY U7, pin 34
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 3.0 A for system startup is recommended.
Power Consumption
The maximum power consumption of a module mainly depends on the design which is running on the FPGA.
Power Input Pin
Typical Current
PL_VIN
TBD*
PS_VIN
TBD*
PS_3.3V
TBD*
* TBD - To Be Determined
For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
It is important that all baseboard I/Os are tri-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.
Power Distribution Dependencies
Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).
Power-On Sequence
The TE0745 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.
Voltage Monitor Circuit
The voltages 'VCCPINT' and 'PS_1.8V' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (available on J2-131 or SC-CPLD) to GND. Leave this pin unconnected or connect to VDD (PS_1.8V) when unused.
Power Rails
Power Rail Name
B2B Connector
JM1 Pin
B2B Connector
JM2 Pin
B2B Connector
JM3 Pin
Direction
Notes
PL_VIN
147, 149, 151, 153, 155, 157, 159
-
-
Input
module supply voltage
PS_VIN
-
154, 156, 158
-
Input
module supply voltage
PS_3.3V
-
160
-
Input
module supply voltage
VCCIO12
54, 55
-
-
Input
high range bank I/O voltage
VCCIO13
112, 113
-
-
Input
high range bank I/O voltage
VCCIO33
-
-
115, 120
Input
high performance bank I/O voltage
VCCIO34
-
29, 30
-
Input
high performance bank I/O voltage
VCCIO35
-
87, 88
-
Input
high performance bank I/O voltage
VBAT_IN
146
-
-
Input
RTC (battery-backed) supply voltage
PS_1.8V
-
130
-
Output
internal 1.8V voltage level (Process System)
PL_1.8V
-
-
84,85
Output
internal 1.8V voltage level (FPGA)
Bank Voltages
Bank
Schematic Name
Voltage
Notes
0 (config)
VCCIO_0
PL_1.8V, if R67 is equipped PS_1.8V, if R68 is equipped
-
500 (MIO0)
PS_1.8V
1.8V
-
501 (MIO1)
PS_1.8V
1.8V
-
502 (DDR3)
1.35V
1.35V
-
12 HR
VCCIO_12
User
HR: 1.2V to 3.3V
13 HR
VCCIO_13
User
HR: 1.2V to 3.3V
33 HP
VCCIO_33
User
HP: 1.2V to 1.8V
Board to Board Connectors
This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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