Template Revision 2.9 - on construction Design Name always "TE Series Name" + optional CPLD Name + "CPLD"
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Firmware for PCB CPLD with designator U39. Second CPLD Device in Chain: LCMX02-1200HC
Feature SummarySee Document Change History
Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
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ALERT_N | in | B33 | UP | +3.3V_STB | Digital output . Interrupt or SMBus alert output. Can be configured as a second THERM output. (Pulled up) [U43,U47,U52,U57,U4](TMP461AIRUNT),U61(LM96163CISD/NOPB) |
CPLD_DEBUG0 | A41 | ||||
CPLD_DEBUG1 | A2 | ||||
CPLD_DEBUG2 | B1 | ||||
CPLD_DEBUG3 | A3 | ||||
CPLD_HD0 | B3 | ||||
CPLD_HD1 | B28 | ||||
EN_VCCINT | B22 | ||||
EN_VTT_DDR | A22 | ||||
EN+0.85V_GT_AVCC_PS | B21 | ||||
EN+0.9V_GT_AVCC | B14 | ||||
EN+1.0V | A46 | ||||
EN+1.2V_DDR | A34 | ||||
EN+1.2V_GT_AVTT | B16 | ||||
EN+1.2V_PLL_PS | A15 | ||||
EN+1.3V_MGT_PS | B15 | ||||
EN+1.8V | B13 | ||||
EN+1.8V_AUX | A30 | ||||
EN+1.8V_GT_AVTT_PS | B20 | ||||
EN+2.5V_DDR | A44 | ||||
EN+2V_MGT_PS | A21 | ||||
EN+3.3V | B18 | ||||
EN+5V_BIAS | A17 | ||||
EXT_STATUS_LED_G | B9 | ||||
EXT_STATUS_LED_R | A25 | ||||
FAN_EN | B29 | ||||
FPGA_DONE | A24 | ||||
FTDI_PWR_EN_N | A36 | ||||
FTDI_RX | A35 | ||||
FTDI_TCK | A45 | ||||
FTDI_TDI | A47 | ||||
FTDI_TDO | A48 | ||||
FTDI_TMS | B34 | ||||
FTDI_TX | B27 | ||||
GND | A19 | ||||
GND | A39 | ||||
GND | B11 | ||||
GND | B31 | ||||
GND | C1 | ||||
I2C_SCL_CPLD | B32 | ||||
I2C_SDA_CPLD | A42 | ||||
JTAGEN | B30 | ||||
MIO30_UART0_RXD | A8 | ||||
MIO31_UART0_TXD | A9 | ||||
MIO32_UART1_TXD | B8 | ||||
MIO33_UART1_RXD | B7 | ||||
MR | A26 | ||||
NetU68_B2 | B2 | ||||
PG_VCCINT | B23 | ||||
PG+0.85V_GT_AVCC_PS | B12 | ||||
PG+0.9V_GT_AVCC | A18 | ||||
PG+1.0V | B35 | ||||
PG+1.2V_DDR | A33 | ||||
PG+1.2V_GT_AVTT | A11 | ||||
PG+1.2V_PLL_PS | A28 | ||||
PG+1.3V_MGT_PS | A20 | ||||
PG+1.8V | B25 | ||||
PG+1.8V_AUX | A27 | ||||
PG+1.8V_AUX_PS | B10 | ||||
PG+1.8V_GT_AUX | A13 | ||||
PG+1.8V_GT_AVTT_PS | A16 | ||||
PG+2.5V_DDR | A32 | ||||
PG+2.5V_PL_DDR | A38 | ||||
PG+2V_MGT_PS | A1 | ||||
PG+3.3V | A23 | ||||
PWR_BTN | A12 | ||||
PWR_STAT_GRN | B24 | ||||
PWR_STAT_RED | A31 | ||||
SRST_B | B5 | ||||
TCK | A5 | ||||
TDI | B4 | ||||
TDO | A6 | ||||
THERM_N | A40 | ||||
TMS | A7 |
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
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Work in progress | |||||
All |
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