Template Revision 2.9 - on construction Design Name always "TE Series Name" + optional CPLD Name + "CPLD"
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Firmware for PCB CPLD with designator U39. Second CPLD Device in Chain: LCMX02-1200HC
Feature SummarySee Document Change History
Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
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ALERT_N | in | B33 | UP | +3.3V_STB | Digital output . Interrupt or SMBus alert output. Can be configured as a second THERM output. (Pulled up) [U43,U47,U52,U57,U4](TMP461AIRUNT),U61(LM96163CISD/NOPB) |
CPLD_DEBUG0 | out | A41 | UP | +3.3V_STB | |
CPLD_DEBUG1 | out | A2 | UP | +3.3V_STB | |
CPLD_DEBUG2 | out | B1 | UP | +3.3V_STB | |
CPLD_DEBUG3 | out | A3 | NONE | +3.3V_STB | |
CPLD_HD0 | ? | B3 | UP | +3.3V_STB | |
CPLD_HD1 | ? | B28 | UP | +3.3V_STB | |
EN_VCCINT | out | B22 | DOWN | +3.3V_STB | |
EN_VTT_DDR | out | A22 | +3.3V_STB | ||
EN+0.85V_GT_AVCC_PS | out | B21 | +3.3V_STB | ||
EN+0.9V_GT_AVCC | out | B14 | +3.3V_STB | ||
EN+1.0V | out | A46 | +3.3V_STB | ||
EN+1.2V_DDR | out | A34 | +3.3V_STB | ||
EN+1.2V_GT_AVTT | out | B16 | +3.3V_STB | ||
EN+1.2V_PLL_PS | out | A15 | +3.3V_STB | ||
EN+1.3V_MGT_PS | out | B15 | +3.3V_STB | ||
EN+1.8V | out | B13 | +3.3V_STB | ||
EN+1.8V_AUX | out | A30 | +3.3V_STB | ||
EN+1.8V_GT_AVTT_PS | out | B20 | +3.3V_STB | ||
EN+2.5V_DDR | out | A44 | +3.3V_STB | ||
EN+2V_MGT_PS | out | A21 | +3.3V_STB | ||
EN+3.3V | out | B18 | +3.3V_STB | ||
EN+5V_BIAS | out | A17 | +3.3V_STB | ||
EXT_STATUS_LED_G | out | B9 | +3.3V_STB | ||
EXT_STATUS_LED_R | out | A25 | +3.3V_STB | ||
FAN_EN | out | B29 | +3.3V_STB | ||
FPGA_DONE | in | A24 | +3.3V_STB | ||
FTDI_PWR_EN_N | in | A36 | +3.3V_STB | ||
FTDI_RX | out | A35 | +3.3V_STB | ||
FTDI_TCK | in | A45 | +3.3V_STB | ||
FTDI_TDI | in | A47 | +3.3V_STB | ||
FTDI_TDO | out | A48 | +3.3V_STB | ||
FTDI_TMS | in | B34 | +3.3V_STB | ||
FTDI_TX | in | B27 | +3.3V_STB | ||
GND | -- | A19 | |||
GND | -- | A39 | |||
GND | -- | B11 | |||
GND | -- | B31 | |||
GND | -- | C1 | |||
I2C_SCL_CPLD | B32 | +3.3V_STB | |||
I2C_SDA_CPLD | A42 | +3.3V_STB | |||
JTAGEN | in | B30 | +3.3V_STB | ||
MIO30_UART0_RXD | A8 | +1.8V | |||
MIO31_UART0_TXD | A9 | +1.8V | |||
MIO32_UART1_TXD | B8 | +1.8V | |||
MIO33_UART1_RXD | B7 | +1.8V | |||
MR / POR_B | out | A26 | +3.3V_STB | ||
NetU68_B2 | B2 | ||||
PG_VCCINT | in | B23 | UP | +3.3V_STB | |
PG+0.85V_GT_AVCC_PS | in | B12 | +3.3V_STB | ||
PG+0.9V_GT_AVCC | in | A18 | +3.3V_STB | ||
PG+1.0V | in | B35 | +3.3V_STB | ||
PG+1.2V_DDR | in | A33 | +3.3V_STB | ||
PG+1.2V_GT_AVTT | in | A11 | +3.3V_STB | ||
PG+1.2V_PLL_PS | in | A28 | +3.3V_STB | ||
PG+1.3V_MGT_PS | in | A20 | +3.3V_STB | ||
PG+1.8V | in | B25 | +3.3V_STB | ||
PG+1.8V_AUX | in | A27 | +3.3V_STB | ||
PG+1.8V_AUX_PS | in | B10 | +3.3V_STB | ||
PG+1.8V_GT_AUX | in | A13 | +3.3V_STB | ||
PG+1.8V_GT_AVTT_PS | in | A16 | +3.3V_STB | ||
PG+2.5V_DDR | in | A32 | +3.3V_STB | ||
PG+2.5V_PL_DDR | in | A38 | +3.3V_STB | ||
PG+2V_MGT_PS | in | A1 | +3.3V_STB | ||
PG+3.3V | in | A23 | +3.3V_STB | ||
PWR_BTN | in | A12 | +3.3V_STB | ||
PWR_STAT_GRN | out | B24 | +3.3V_STB | ||
PWR_STAT_RED | out | A31 | +3.3V_STB | ||
SRST_B | inout | B5 | +1.8V | ||
TCK | out | A5 | +1.8V | ||
TDI | out | B4 | +1.8V | ||
TDO | in | A6 | +1.8V | ||
THERM_N | in | A40 | +3.3V_STB | ||
TMS | out | A7 | +1.8V |
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
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Work in progress | |||||
All |
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