Template Revision 3.0 Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Zynq PS Design with Linux Example and 2 ETH (On board and TE0706 ETH PHY).
Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Design supports following carriers:
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - Xilinx devices
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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Not used on this Example.
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder
Monitoring: PHY LED
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Type | Note |
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DDR | --- |
QSPI | MIO |
ETH0 | MIO |
ETH1 | EMIO |
USB0 | MIO |
SD0 | MIO |
SD1 | MIO |
UART0 | MIO |
UART1 | MIO |
I2C0 | MIO |
I2C1 | EMIO |
GPIO | MIO |
TTC0..1 | EMIO |
WDT | EMIO |
# # Common BITGEN related settings for TE0720 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design |
# set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
# # Constraints for System controller support logic # set_property PACKAGE_PIN K16 [get_ports PL_pin_K16] set_property PACKAGE_PIN K19 [get_ports PL_pin_K19] set_property PACKAGE_PIN K20 [get_ports PL_pin_K20] set_property PACKAGE_PIN L16 [get_ports PL_pin_L16] set_property PACKAGE_PIN M15 [get_ports PL_pin_M15] set_property PACKAGE_PIN N15 [get_ports PL_pin_N15] set_property PACKAGE_PIN N22 [get_ports PL_pin_N22] set_property PACKAGE_PIN P16 [get_ports PL_pin_P16] set_property PACKAGE_PIN P22 [get_ports PL_pin_P22] # # If Bank 34 is not 3.3V Powered need change the IOSTANDARD # set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
############################################################ # 34_L13_N JB3:33 PHY:IN set_property PACKAGE_PIN M20 [get_ports {ENET1_EXT_INTIN_0}] set_property IOSTANDARD LVCMOS33 [get_ports ENET1_EXT_INTIN_0] ############################################################ # B34_L8_P JB3:38 RGMII_td[3] set_property PACKAGE_PIN J21 [get_ports {RGMII_td[3]}] # B34_L8_N JB3:40 RGMII_td[2] set_property PACKAGE_PIN J22 [get_ports {RGMII_td[2]}] # B34_L9_P JB3:42 RGMII_td[1] set_property PACKAGE_PIN J20 [get_ports {RGMII_td[1]}] # B34_L9_N JB3:44 RGMII_td[0] set_property PACKAGE_PIN K21 [get_ports {RGMII_td[0]}] set_property IOSTANDARD LVCMOS33 [get_ports RGMII_td*] ## B34_L22_P JB3:58 RGMII_rxc #set_property PACKAGE_PIN R19 [get_ports RGMII_rxc] #set_property IOSTANDARD LVCMOS33 [get_ports RGMII_rxc] ## B34_L22_N JB3:60 ETH_CONFIG set_property PACKAGE_PIN T19 [get_ports {ETH_CONFIG[0]}] set_property IOSTANDARD LVCMOS33 [get_ports ETH_CONFIG*] ## B34_L12_N JB3:32 CLK_R_125 set_property PACKAGE_PIN L18 [get_ports {gmii_clk_0}] set_property IOSTANDARD LVCMOS33 [get_ports gmii_clk_0] #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {gmii_clk_0_IBUF}] ############################################################ # B34_L13_P JB3:31 RGMII_rxc set_property PACKAGE_PIN M19 [get_ports RGMII_rxc] set_property IOSTANDARD LVCMOS33 [get_ports RGMII_rxc] # B34_L21_P JB3:37 RGMII_rd[3] set_property PACKAGE_PIN T16 [get_ports {RGMII_rd[3]}] # B34_L21_N JB3:39 RGMII_rd[2] set_property PACKAGE_PIN T17 [get_ports {RGMII_rd[2]}] # B34_L15_P JB3:41 RGMII_rd[1] set_property PACKAGE_PIN M21 [get_ports {RGMII_rd[1]}] # B34_L15_N JB3:43 RGMII_rd[0] set_property PACKAGE_PIN M22 [get_ports {RGMII_rd[0]}] set_property IOSTANDARD LVCMOS33 [get_ports RGMII_rd*] # B34_L17_P JB3:47 RGMII_rx_ctl set_property PACKAGE_PIN R20 [get_ports RGMII_rx_ctl] set_property IOSTANDARD LVCMOS33 [get_ports RGMII_rx_ctl] # B34_L17_N JB3:49 MDIO_PHY_mdc set_property PACKAGE_PIN R21 [get_ports MDIO_PHY_mdc] set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_mdc] # B34_L23_P JB3:51 mdio_phy_mdio_io set_property PACKAGE_PIN R18 [get_ports MDIO_PHY_mdio_io] set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_mdio_io] # B34_L23_N JB3:53 ETH_RST set_property PACKAGE_PIN T18 [get_ports {ETH_RST[0]}] set_property IOSTANDARD LVCMOS33 [get_ports ETH_RST*] # B34_L14_P JB3:57 RGMII_txc set_property PACKAGE_PIN N19 [get_ports RGMII_txc] set_property IOSTANDARD LVCMOS33 [get_ports RGMII_txc] # B34_L14_N JB3:59 RGMII_tx_ctl set_property PACKAGE_PIN N20 [get_ports RGMII_tx_ctl] set_property IOSTANDARD LVCMOS33 [get_ports RGMII_tx_ctl] ############################################################ #timing #create_clock -period 8.000 -name RGMII_rxc -waveform {0.000 4.000} [get_ports RGMII_rxc] #set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {*gmii_clk_25m_out *gmii_clk_2_5m_out}] -group [get_clocks -include_generated_clocks *gmii_clk_125m_out] #ignore vio set_false_path -from [get_pins -hier -filter {name =~ */i_gmii_to_rgmii/i_gmii_to_rgmii/link_status_reg/C}] -to [get_pins -hier -filter {name =~ */PROBE_IN_INST/probe_in_reg_reg*/D}] set_false_path -from [get_pins -hier -filter {name =~ */i_gmii_to_rgmii/i_gmii_to_rgmii/clock_speed_reg[*]/C}] -to [get_pins -hier -filter {name =~ */PROBE_IN_INST/probe_in_reg_reg*/D}] set_false_path -from [get_pins -hier -filter {name =~ */i_gmii_to_rgmii/i_gmii_to_rgmii/duplex_status_reg/C}] -to [get_pins -hier -filter {name =~ */PROBE_IN_INST/probe_in_reg_reg*/D}] ## Clock Period Constraints #create_clock -period 5.000 -name clkin -add [get_nets clkin] create_clock -period 8.000 -name rgmii_rxc -add [get_ports RGMII_rxc] ## Clock constraint if parameter C_EXTERNAL_CLOCK = 1 #create_clock -add -name gmii_clk -period 8.000 [get_ports gmii_clk] ## Clock constraint if parameter C_EXTERNAL_CLOCK = 1 and clock skew on TXC is through MMCM #create_clock -add -name gmii_clk_90 -period 8.000 -waveform {2 6} [get_ports gmii_clk_90] ##False path constraints to async inputs coming directly to synchronizer set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_reset_gen/*reset_sync*/PRE }] set_false_path -to [get_pins -of [get_cells -hier -filter { name =~ *i_MANAGEMENT/SYNC_*/data_sync* }] -filter { name =~ *D }] set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] ##False path constraints from Control Register outputs set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/DUPLEX_MODE_REG*/C }] set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/SPEED_SELECTION_REG*/C }] ## constraint valid if parameter C_EXTERNAL_CLOCK = 0 set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/CE0}] set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/S0}] set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/CE1}] set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/S1}] ## constraint valid if parameter C_EXTERNAL_CLOCK = 0 and clock skew on TXC is through MMCM #set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/CE0}] #set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/S0}] #set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/CE1}] #set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/S1}] #... set_property slew FAST [get_ports [list {RGMII_td[3]} {RGMII_td[2]} {RGMII_td[1]} {RGMII_td[0]} RGMII_txc RGMII_tx_ctl]] |
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For SDK project creation, follow instructions from:
---------------------------------------------------------- FPGA Example todo.. ---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2018.3 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2018.3 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2018.3 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
TE modified 2019.2 FSBL
General:
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
Module Specific:
TE modified 2019.2 FSBL
General:
Hello World App in Endless loop.
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO_MMC \ "dfu_mmc_info=" \ "set dfu_alt_info " \ "${kernel_image} fat 0 1\\\\;" \ "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" /*Required for uartless designs */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #ifdef CONFIG_DEBUG_UART #undef CONFIG_DEBUG_UART #endif #endif /*Dependencies for ENV to be stored in EEPROM. Ensure environment fits in eeprom size*/ #ifdef CONFIG_ENV_IS_IN_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ #define CONFIG_SYS_I2C_MUX_ADDR 0x74 #define CONFIG_SYS_I2C_MUX_EEPROM_SEL 0x4 #endif #define CONFIG_PREBOOT "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp" |
/include/ "system-conf.dtsi" / { }; /* default */ /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; }; /* ETH PHY from TE0706*/ &gem1 { // local-mac-address = [00 0a 35 00 db b2]; phy-handle = <&phy1>; mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <1>; //marvell,reg-init = <0x3 0x10 0x0000 0x0501 0x3 0x11 0x0000 0x4415>; marvell,reg-init = <0x12 0x14 0x0200>; }; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; /* I2C need I2C1 connected to te0720 system controller ip */ &i2c1 { iexp@20 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x20>; gpio-controller; }; iexp@21 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x21>; gpio-controller; }; rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; |
Start with petalinux-config -c kernel
Changes:
Add manually
Changes:
Start with petalinux-config -c rootfs
Changes:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Webserver application accemble for Zynq access. Need busybox-httpd
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No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
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