Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


Date

Version

Changes

Author

2023-12-143.1.17
  • updated according to Vivado 2023.2
ma
2023-06-133.1.16
  • Design flow:
    • added alternative programming files in Petalinux
  • added chapter FSBL Patch in Software Design - Petalinux
ma
2023-06-013.1.15
  • removed u-boot.dtb from Design flow
ma
2023-06-013.1.14
  • expandable lists for revision history and supported hardware
wh
2023-05-253.1.13
  • updated according to Vivado 2022.2
ma
2023-02-083.1.12
  • removed content of
    • Special FSBL for QSPI programming
ma
2022-08-243.1.11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh

2021-06-28

3.1.8

  • added boot process for Microblaze

  • minor typos, formatting

ma

2021-06-01

3.1.7

  • carrier reference note

jh

2021-05-04

3.1.6

  • removed zynq_ from zynq_fsbl

ma

2021-04-28

3.1.5

  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export

  • minor typos, formatting

ma

2021-04-27

3.1.4

  • Version History

    • changed from list to table

  • Design flow

    • removed step 5 from Design flow

    • changed link from TE Board Part Files to Vivado Board Part Flow

    • changed cmd shell from picture to codeblock

    • added hidden template for "Copy PetaLinux build image files", depending from hardware

    • added hidden template for "Power on PCB", depending from hardware

  • Usage update of boot process

  • Requirements - Hardware

    • added "*used as reference" for hardware requirements

  • all

    • placed a horizontal separation line under each chapter heading

    • changed title-alignment for tables from left to center

  • all tables

    • added "<project folder>\board_files" in Vivado design sources

ma


3.1.3

  • Design Flow

    • formatting

  • Launch

    • formatting

ma


3.1.2

  • minor typing corrections

  • replaced SDK by Vitis

  • changed from / to \ for windows paths

  • replaced <design name> by <project folder>

  • added "" for path names

  • added boot.src description

  • added USB for programming

ma


3.1.1

  • swapped order from prebuilt files

  • minor typing corrections

  • removed Win OS path length from Design flow, added as caution in Design flow

ma


3.1

  • Fix problem with pdf export and side scroll bar

  • update 19.2 to 20.2

  • add prebuilt content option



3.0

  • add fix table of content

  • add table size as macro

  • removed page initial creator



Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template (note: inner scroll ignore/only only with drawIO object):


        Create DrawIO object here: Attention if you copy from other page, use


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)


      • Example

        Comment

        1

        2



  • ...

Overview


Notes :

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.

Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • Add basic key futures, which can be tested with the design


  • Vitis/Vivado 2023.2

  • QSPI

  • Custom Carrier (minimum PS Design with available module components only)

  • Modified FSBL (some additional outputs only)

Revision History

Notes :

  • add every update file on the download

  • add design changes on description

Date

Vivado

Project Built

Authors

Description

2024-03-012023.2TE0813-test_board-vivado_2023.2-build_4_20240301164142.zip
TE0813-test_board_noprebuilt-vivado_2023.2-build_4_20240301164142.zip		Manuela Strücker
  • update Vivado 2023.2
  • new variants
2023-09-262022.2TE0813-test_board-vivado_2022.2-build_9_20230926222100.zip
TE0813-test_board_noprebuilt-vivado_2022.2-build_9_20230926222100.zip		Manuela Strücker
  • new variants
2023-06-212022.2TE0813-test_board_noprebuilt-vivado_2022.2-build_2_20230621091607.zip
TE0813-test_board-vivado_2022.2-build_2_20230621091607.zip		John Hartfiel
  • update Vivado 2022.2
  • new variants
  • script update
2022-10-182021.2.1TE0813-test_board_noprebuilt-vivado_2021.2-build_18_20221018115000.zip
TE0813-test_board-vivado_2021.2-build_18_20221018115000.zip		Manuela Strücker
  • update Vivado 2021.2.1
  • new variants
  • script update
2021-11-162020.2TE0813-test_board_noprebuilt-vivado_2020.2-build_9_20211116073725.zip
TE0813-test_board-vivado_2020.2-build_9_20211116073013.zip		John Hartfiel
  • new variants
2021-10-282020.2TE0813-test_board-vivado_2020.2-build_8_20211028144436.zip
TE0813-test_board_noprebuilt-vivado_2020.2-build_8_20211028144418.zip		Manuela Strücker
  • initial release



Release Notes and Know Issues

Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed


IssuesDescriptionWorkaroundTo be fixed version
Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
QSPI FlashProgramming QSPI flash fails sometimesuse Vivado 2019.2 for programming


Requirements

Software

Notes :

  • list of software which was used to generate the design


SoftwareVersionNote
Vitis2023.2needed, Vivado is included into Vitis installation



Hardware

Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0813-01-2AE11-A2cg_1e_2gbREV012GB128MBNANANA
TE0813-01-2AE11-AZ2cg_1e_2gbREV012GB128MBNANANA
TE0813-01-2AE11-KZ2cg_1e_2gbREV012GB128MBNANANA
TE0813-01-2BE11-A2eg_1e_2gbREV012GB128MBNANANA
TE0813-01-3AE11-A3cg_1e_2gbREV012GB128MBNANANA
TE0813-01-3BE11-A3eg_1e_2gbREV012GB128MBNANANA
TE0813-01-4AE11-A4cg_1e_2gbREV012GB128MBNANANA
TE0813-01-4BE11-A4eg_1e_2gbREV012GB128MBNANANA
TE0813-01-4BE11-AZ4eg_1e_2gbREV012GB128MBNANANA
TE0813-01-4BE71-A4eg_1e_4gbREV014GB128MBNANANA
TE0813-01-4BE71-AZ4eg_1e_4gbREV014GB128MBNANANA
TE0813-01-4BE81-A4eg_1e_4gbREV014GB128MBNANANA
TE0813-01-4BE81-AZ4eg_1e_4gbREV014GB128MBNANANA
TE0813-01-4DE11-A4ev_1e_2gbREV012GB128MBNANANA
TE0813-01-4DE11-AZ4ev_1e_2gbREV012GB128MBNANANA
TE0813-01-5DE11-A5ev_1e_2gbREV012GB128MBNANANA
TE0813-01-S0032cg_1e_2gbREV012GB128MBNANAwithout PLL
TE0813-02-2AE81-A2cg_1e_4gbREV024GB128MBNANANA
TE0813-02-2AE81-AK2cg_1e_4gbREV024GB128MBNANANA
TE0813-02-2BE81-A2eg_1e_4gbREV024GB128MBNANANA
TE0813-02-3AE81-A3cg_1e_4gbREV024GB128MBNANANA
TE0813-02-3BE81-A3eg_1e_4gbREV024GB128MBNANANA
TE0813-02-4AE81-A4cg_1e_4gbREV024GB128MBNANANA
TE0813-02-4BE71-A4eg_1e_4gbREV024GB128MBNANANA
TE0813-02-4BE81-A4eg_1e_4gbREV024GB128MBNANANA
TE0813-02-4DE81-A4ev_1e_4gbREV024GB128MBNANANA
TE0813-02-5DE81-A5ev_1e_4gbREV024GB128MBNANANA
TE0813-02-5DI81-A5ev_1i_4gbREV024GB128MBNANANA
TE0813-02-S0014eg_1i_8gbREV028GB128MBNANANA

*used as reference

Note: Design contains also Board Part Files for TE0813+TEBF0818 configuration, this board part files are not used for this reference design.

Design supports following carriers:

Carrier Model

Notes

TEBF0818*

Used as reference carrier.

*used as reference

Additional HW Requirements:

Additional Hardware

Notes

---

---

*used as reference

Content

Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files		Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation



Additional Sources

Type

Location

Notes

---

---

---


Prebuilt

Notes :

  • prebuilt files
  • Template Table:


    • File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems





File

File-Extension

Description

BIF-File

*.bif

File with description to generate Bin-File

BIN-File

*.bin

Flash Configuration File with Boot-Image (Zynq-FPGAs)

BIT-File

*.bit

FPGA (PL Part) Configuration File

Diverse Reports

---

Report files in different formats

Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux

LabTools Project-File

*.lpr

Vivado Labtools Project File

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow


Notes :

  • Basic Design Steps

  • Add/ Remove project specific description


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")


  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    ------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0)  Module selection guide, project creation...prebuilt export...
-- (1)  Create minimum setup of CMD-Files and exit Batch
-- (2)  Create maximum setup of CMD-Files and exit Batch
-- (3)  (internal only) Dev
-- (4)  (internal only) Prod
-- (c)  Go to CMD-File Generation (Manual setup)
-- (d)  Go to Documentation (Web Documentation)
-- (g)  Install Board Files from Xilinx Board Store (beta)
-- (a)  Start design with unsupported Vivado Version (beta)
-- (x)  Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"

  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.

    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

      Important: Use Board Part Files, which did not ends with *_tebf0818


  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    TE::hw_build_design -export_prebuilt


    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Generate Programming Files with Vitis

    TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


Launch


Note:

  • Programming and Startup procedure

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection

    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

  1. Connect JTAG and power on carrier with module

  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    TE::pr_program_flash -swapp hello_te0813


    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup



SD-Boot mode

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with Vitis Debugger into device

Usage

QSPI Boot:

  1. Prepare HW like described on section Programming

  2. Connect UART USB (most cases same as JTAG)

  3. Select QSPI as Boot Mode

    Note: See TRM of the Carrier, which is used.


  4. Power On PCB

    1. ZynqMP Boot ROM loads FSBL from QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR,


System Design - Vivado


Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design


PS Interfaces

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

Type

Note

DDR


QSPI

MIO

UART0

MIO, please select other one, if you have connected UART to second controller or other MIO

SWDT0..1


TTC0..3



Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - Vitis


Note:

  • optional chapter separate

  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2023.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY


----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name


Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • OTG+PCIe Reset over MIO
    • I2C MUX for EEPROM MAC

hello_te0813

Hello TE0813 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software


Note:

  • Add description for other Software, for example SI CLK Builder ...

  • SI5338 and SI5345 also Link to:

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports



Date

Document Revision

Authors

Description

  • update Vivado 2023.2

  • new Variants

2023-09-27

v.12

Manuela Strücker
  • new Variants

2023-08-14

v.11

Manuela Strücker

  • update Vivado 2022.2

  • new Variants

  • script update

2022-10-20

v.6

Manuela Strücker

  • update Vivado 2021.2.1

  • new Variants

  • script update
2022-09-06v5Manuela Strücker
  • new Variants
2021-10-28v.2Manuela Strücker
  • initial release 2020.2

All




Legal Notices





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