Description: 

From time to time problems with PCIe on some TEBF0808/TE080x combinations are reported. The problems can have various causes and are usually one or a combination of the following:

• 72992 - Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Possible link training failures or data errors on PCIe, SATA, or USB 3.0 protocol links using PS GTR
  • Xilinx provides patches for older Vivado Versions, Vivado 2021.1 or newer should be fixed (Status 22.03.22 → Xilinx has changed this one time, so please check always AR#72992)
• TE080x PCIe Reference Clock initialisation will be done mostly via I2C on FSBL. Xilinx provides custom access on FSBL after MIO and GTR initialisation. PLL initialisation before GTR initialisation will improve the initialisation of the link:
  • Trenz Electronic provides special FSBL inside Xilinx PSU (between MIO initialisation and GTR initialisation) to solve this problem. This is done since Vivado 18.3 reference design releases.
• Alignment Problems with SS5, ST5 connectors, which can cause connection problems:
  • Trenz Electronic has improved production to minimize tolerances.
  • Trenz Electronic starts to publish new Series TE081X which has same functionality but uses ADM6 connectors, which have very good self alignment capabilities.
• PCIe Reference CLK can cause problem with PCIe:
  • SoC/FPGA side: Xilinx GTR reference CLK supports LVDS/LVPECL. PLL will be configured with correct LVDS standard on Trenz Reference Designs. In case of custom carrier and external reference clock, see also Xilinx ARx43641.
  • PCIe Card side: PCIe requires HCSL IO or similar standard. Currently on the TEBF0808 AC coupled LVDS is used, which is generated by the PLL of the module. However, the PLLs (SI5338 of SI5345) also support HCSL .  SI5338 has internal termination and SI5345 require external termination for HCSL.
    • Trenz plan to update TEBF0808 to revision 05 with  LVDS to HCSL multiplexer.
    • For older Revisions, still use LVDS or in case of TE0803, it's possibke to archive better results when the PLL is changed to HCSL and the capacitors on the carrier are replaced by 0Ohm resistors in case.

Products Affected

This AVN affects all Trenz Electronic TEBF0808 together with compatible SoMs: TE080x.

Advices

#1 Use HSCL standard for PCIe CLK

Type: Improvement
Reason: HSCL standard is more in compliance with PCIe specification and will improve PCIe stability.
Impact: Carrier which still use AC coupled reference CLK for PCIe on the carrier are recommended to be modify, see #2. Changes will be implemented in newer reference designs (2021.2 or newer)

#2 Replace C93 and C94 by 0Ohm resistor

Type: Improvement
Reason: DC coupled HSCL standard is more in compliance with PCIe specification and will improve PCIe stability.  Capacitor C93 and C94 of PCI_REF_*/CLK0_* should be replaced with 0Ohm resistor
Impact: Design which still use LVDS as PLL output for PCIe CLK to the carrier are recommended to be configured to use HSCL, see #1.

Method of Identification

• #1: Check PLL project files of your design
  TE0808/TE0807:
  
  TE0803:
  
  
  
• #2: Check TEBF0808 PCN and assembly  option of C93/C94 on the carrier.
  

This AVN follows JEDEC Standard J-STD-046.