Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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Refer to http://trenz.org/te0727-info for the current online version of this manual and other available documentation.
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Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
*used as reference |
Design supports following carriers:
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Additional HW Requirements:
*used as reference |
Notes :
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
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Notes :
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Notes :
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
Press 0 and enter to start "Module Selection Guide"
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for ...
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Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Note:
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Boot.bin on QSPI Flash and image.ub and boot.scr on SD.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0727 (optional) |
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot (fsbl, u-boot) and SD for secondary boot (image.ub, boot.src)
Not used on this Example.
Prepare HW like described in section Programming
Connect UART USB (most cases same as JTAG)
Insert SD Card with image.ub and boot.src
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ... |
Open Serial Console (e.g. putty)
Speed: 115200
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
petalinux login: root Password: root |
Note: Wait until Linux boot finished |
You can use Linux shell now.
i2cdetect -y -r 1 (check I2C (Bus 0...2 possible)) lsusb (USB check) |
Camera stream will be enabled via init.sh script on SD
Take image from camera (must be enabled with init.sh script):
fbgrab -d /dev/fb0 /run/media/sda1/camera.png (write image to USB Stick) |
Note:
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Note:
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Activated interfaces:
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# # Common BITGEN related settings for TE0727 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] |
# # # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
set_property PACKAGE_PIN G11 [get_ports {CEC_A[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {CEC_A[0]}] set_property PACKAGE_PIN H13 [get_ports {HPD_A}] set_property IOSTANDARD LVCMOS33 [get_ports {HPD_A}] set_property PACKAGE_PIN G14 [get_ports {GLED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {GLED[0]}] set_property PACKAGE_PIN G12 [get_ports {IIC_A_scl_io}] set_property PACKAGE_PIN H12 [get_ports {IIC_A_sda_io}] set_property IOSTANDARD LVCMOS33 [get_ports {IIC_A_*}] set_property PACKAGE_PIN K12 [get_ports {CT_HPD[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {CT_HPD[0]}] set_property PACKAGE_PIN F12 [get_ports {HDMI_TXC_P}] set_property PACKAGE_PIN E13 [get_ports {HDMI_TXC_N}] set_property PACKAGE_PIN E11 [get_ports {HDMI_TX_P[0]}] set_property PACKAGE_PIN E12 [get_ports {HDMI_TX_N[0]}] set_property PACKAGE_PIN G15 [get_ports {HDMI_TX_P[1]}] set_property PACKAGE_PIN F15 [get_ports {HDMI_TX_N[1]}] set_property PACKAGE_PIN F14 [get_ports {HDMI_TX_N[2]}] set_property PACKAGE_PIN F13 [get_ports {HDMI_TX_P[2]}] set_property IOSTANDARD TMDS_33 [get_ports {HDMI_*}] set_property PACKAGE_PIN J11 [get_ports {GPIO_tri_io[0]}] set_property PACKAGE_PIN H11 [get_ports {GPIO_tri_io[1]}] set_property PACKAGE_PIN J15 [get_ports {GPIO_tri_io[2]}] set_property PACKAGE_PIN L15 [get_ports {GPIO_tri_io[3]}] set_property PACKAGE_PIN N13 [get_ports {GPIO_tri_io[4]}] set_property PACKAGE_PIN P8 [get_ports {GPIO_tri_io[5]}] set_property PACKAGE_PIN M10 [get_ports {GPIO_tri_io[6]}] set_property PACKAGE_PIN L12 [get_ports {GPIO_tri_io[7]}] set_property PACKAGE_PIN M11 [get_ports {GPIO_tri_io[8]}] set_property PACKAGE_PIN P10 [get_ports {GPIO_tri_io[9]}] set_property PACKAGE_PIN P9 [get_ports {GPIO_tri_io[10]}] set_property PACKAGE_PIN K15 [get_ports {GPIO_tri_io[11]}] set_property PACKAGE_PIN M9 [get_ports {GPIO_tri_io[12]}] set_property PACKAGE_PIN L13 [get_ports {GPIO_tri_io[13]}] set_property PACKAGE_PIN L14 [get_ports {GPIO_tri_io[14]}] set_property PACKAGE_PIN M15 [get_ports {GPIO_tri_io[15]}] set_property PACKAGE_PIN J14 [get_ports {GPIO_tri_io[16]}] set_property PACKAGE_PIN N14 [get_ports {GPIO_tri_io[17]}] set_property PACKAGE_PIN K11 [get_ports {GPIO_tri_io[18]}] set_property PACKAGE_PIN N9 [get_ports {GPIO_tri_io[19]}] set_property PACKAGE_PIN J13 [get_ports {GPIO_tri_io[20]}] set_property PACKAGE_PIN H14 [get_ports {GPIO_tri_io[21]}] set_property PACKAGE_PIN R10 [get_ports {GPIO_tri_io[22]}] set_property PACKAGE_PIN M14 [get_ports {GPIO_tri_io[23]}] set_property PACKAGE_PIN P15 [get_ports {GPIO_tri_io[24]}] set_property PACKAGE_PIN M12 [get_ports {GPIO_tri_io[25]}] set_property PACKAGE_PIN K13 [get_ports {GPIO_tri_io[26]}] set_property PACKAGE_PIN R15 [get_ports {GPIO_tri_io[27]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_io*}] set_property PACKAGE_PIN N12 [get_ports {CSI_C_N}] set_property PACKAGE_PIN N11 [get_ports {CSI_C_P}] set_property PACKAGE_PIN R8 [get_ports {CSI_D_N[0]}] set_property PACKAGE_PIN R7 [get_ports {CSI_D_P[0]}] set_property PACKAGE_PIN R13 [get_ports {CSI_D_N[1]}] set_property PACKAGE_PIN R12 [get_ports {CSI_D_P[1]}] set_property IOSTANDARD LVDS_25 [get_ports {CSI_*}] set_property PACKAGE_PIN N8 [get_ports {CLP_D_N[0]}] set_property PACKAGE_PIN N7 [get_ports {CLP_D_P[0]}] set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}] set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}] #set_property PACKAGE_PIN R11 [get_ports {CLP_C_N}] #set_property PACKAGE_PIN P11 [get_ports {CLP_C_P}] set_property IOSTANDARD HSUL_12 [get_ports {CLP_*}] set_property PULLDOWN true [get_ports {CLP_*}] set_property INTERNAL_VREF 0.6 [get_iobanks 34] create_clock -period 6.250 -name csi_clk -add [get_ports CSI_C_P] |
set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_N[1]}] set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_N[0]}] set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_P[1]}] set_property IOSTANDARD HSUL_12 [get_ports {CLP_D_P[0]}] set_property IOSTANDARD LVDS_25 [get_ports {CSI_D_P[1]}] set_property IOSTANDARD LVDS_25 [get_ports {CSI_D_P[0]}] set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}] set_property PACKAGE_PIN N8 [get_ports {CLP_D_N[0]}] set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}] set_property PACKAGE_PIN N7 [get_ports {CLP_D_P[0]}] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] connect_debug_port dbg_hub/clk [get_nets clk] |
Note:
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
TE modified 2020.2 FSBL
General:
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
Module Specific:
TE modified 2020.2 FSBL
General:
Hello TE0727 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
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Start with petalinux-config or petalinux-config --get-hw-description
Changes:
No changes
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
Change platform-top.h:
#include <configs/zynq-common.h> #include <configs/platform-auto.h> |
/include/ "system-conf.dtsi" / { }; / { #address-cells = <1>; #size-cells = <1>; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; // HDMI Output frame buffer hdmi_fb_reserved_region@1FC00000 { compatible = "removed-dma-pool"; no-map; // 512M (M modules) reg = <0x1FC00000 0x400000>; // 128M (R modules) //reg = <0x7C00000 0x400000>; }; /* // Use second frame buffer if you want separate area for camera image camera_fb_reserved_region@1FC00000 { compatible = "removed-dma-pool"; no-map; // 512M (M modules) reg = <0x1FC00000 0x400000>; // 128M (R modules) //reg = <0x7800000 0x400000>; }; */ }; hdmi_fb: framebuffer@0x1FC00000 { // HDMI out compatible = "simple-framebuffer"; // 512M (M modules) reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p // 128M (R modules) //reg = <0x7C00000 (1280 * 720 * 4)>; // 720p width = <1280>; // 720p height = <720>; // 720p stride = <(1280 * 4)>; // 720p format = "a8b8g8r8"; status = "okay"; }; /* // In "go through" mode only one framebuffer is used camera_fb: framebuffer@0x1FC00000 { // CAMERA in compatible = "simple-framebuffer"; // 512M (M modules) reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p // 128M (R modules) //reg = <0x7800000 (1280 * 720 * 4)>; // 720p width = <1280>; // 720p height = <720>; // 720p stride = <(1280 * 4)>; // 720p format = "a8b8g8r8"; }; */ vcc_3V3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vccaux-supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* * We need to disable Linux VDMA driver as VDMA * already configured in FSBL */ &video_out_axi_vdma_0 { // Solution 1: Disable standard VDMA driver (VDMA configuration should be done in the FSBL) status = "disabled"; // Solution 2: Configure VDMA using the custom driver (VDMA configuration in FSBL should be disabled) //compatible = "trenz,vdmafb"; //width = <1280>; //height = <720>; //stride = <(1280 * 4)>; //format = "a8b8g8r8"; }; &video_in_axi_vdma_0 { // Solution 1: Disable satandard VDMA driver (VDMA configuration should be done in the FSBL) status = "disabled"; }; &gpio0 { interrupt-controller; #interrupt-cells = <2>; }; /* I2C1 - for REV02 */ &i2c1 { #address-cells = <1>; #size-cells = <0>; i2cmux: i2cmux@70 { compatible = "nxp,pca9540"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; ID_I2C@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; CSI_I2C@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; }; }; /* USB */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { usb-phy = <&usb_phy0>; } ; |
Must be add manually, see template
Start with petalinux-config -c kernel
Changes:
CONFIG_FB_SIMPLE=y
# CONFIG_FRAMEBUFFER_CONSOLE is not set
Change linux-xlnx_%.bbappend:
FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" SRC_URI += "file://devtool-fragment.cfg \ file://0001-QSPI-s25fl127_8-2020_2.patch \ " |
Start with petalinux-config -c rootfs
Changes:
CONFIG_i2c-tools=y
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Script App to load init.sh from SD Card if available.
Application used to enable and configure Raspbery Pi camera module
Application used to take screenshot from camera
Note: |
No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
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