The Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.
Vivado is recommended for all Trenz Electronics products that are based on Xilinx 7 or UltraScale+ series. Trenz Electronics supplies Vivado Board Part Files for all products supported by Vivado.
Table of contents
|2021.2***,****||Xilinx AR#76539||Xilinx AR#76498||Xilinx AR#000032521|
|2020.2||Xilinx AR#75186||Xilinx AR#73646||Xilinx AR#75775|
|2019.2**||Xilinx AR#72162||Xilinx AR#72773||Xilinx AR#72950|
|2017.4**||Xilinx AR#69697||Xilinx AR#70277|
|2016.4||Xilinx AR#66830||Xilinx AR#68370|
|2016.2||Xilinx AR#66830||Xilinx AR#66230||Xilinx AR#67409|
Note: * AR# 69908: 2017.1...3 - Vivado does not launch with Windows 10 Fall Creators Update
** AR#70146: QSPI flash programming now requires that you specify an FSBL, AR#70548: Zynq-7000 - QSPI programming in QSPI-boot mode -Trenz Electronic will provide special FSBL on 2017.4 an newer reference design.
*** Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request
**** Since 2021.2, Xilinx add Versal to Vivado as default installation. In case Versal is not used, Vivado installation size can be reduced around 40GB, when this folder will be deleted: C:\Xilinx\Vivado\2021.2\data\parts\xilinx\devint\vault
|UltraScale+ RFSoC||EN#291 (PDF)|
Zynq UltraScale+ RFSoC Production Errata
|UltraScale+ Zynq||Xilinx AR#68750||Zynq UltraScale+ MPSoC - Errata Work-around Solutions|
Zynq-7000 SoC - Errata Work-around Solutions
|7 Series||Xilinx AR#46370|
Xilinx 7 Series FPGA Solution Center
Xilinx Zynq UltraScale+ MPSoC Solution Center
Xilinx Zynq-7000 SoC Solution Center
Xilinx 7 Series FPGA Solution Center
It's recommended to use Xilinx Documentation Navigator (DocNav) to get access to all documentation of Xilinx with "Up to Date Catalog" of DocNav. Documents can be found easy by "DOC ID" via search function of the catalog view. Search documents on Web is also possible, but ensure to use the appropriate document version to your installed Xilinx software.
|All||Vivado Design Suite User Guide: Programming and Debugging||UG908||Documents Vivado® tools for programming and debugging a Xilinx® FPGA design. Programming the FPGA includes generating a bitstream file from the implemented design and downloading the file to the target device. Also describes how to debug a design including RTL simulation and in-system debugging.|
Zynq, Artix, Kintex, Virtex
|Vivado Design Suite Tutorial: Embedded Processor Hardware Design||UG940|
Demonstrates building a Zynq®-7000 All Programmable SoC processor-based design and a Microblaze™ processor design in the Vivado® tools. Uses the Vivado IP integrator to build a design and then debug the design with the Xilinx® Software Development Kit (SDK) and the Vivado logic analyzer.
|ZynqMP||Zynq UltraScale+ MPSoC: Embedded Design Tutorial||UG1209||Demonstrates building a Zynq UltraScale+ MPSoC processor-based embedded design using Vivado® Design Suite and the Xilinx® Software Development Kit. Provides a hands-on tutorial for effective embedded system design.|
|Dev-Guide||UltraFast Design Methodology Guide for the Vivado Design Suite||UG949|
Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions.
UltraFast Embedded Design Methodology Guide
Describes the recommended design methodology for embedded designs using the Vivado® Design Suite and Xilinx SDK. Provides the reasons behind the recommended method to support and enable informed design decisions.
Vivado Design Suite User Guide - Using the Vivado IDE
|UG893||Describes the Vivado® Integrated Design Environment (IDE), providing an intuitive graphical user interface (GUI) to visualize and interact with an FPGA design. Describes how the Vivado IDE helps you configure tool options, analyze and refine timing, and floorplan a design to improve results.|
|Dev-Guide||Vivado Design Suite User Guide - Embedded Processor Hardware Design||UG898||Discusses using the Vivado IP Integrator and Xilinx Software Development Kit (SDK) to design and debug microprocessor-based systems and embedded software applications using the Zynq®-7000 All Programmable (AP) SoC, Zynq UltraScale+™ MPSoC, or the MicroBlaze™ processor.|
Vitis Unified Software Platform Documentation - Embedded Software Development
The Vitis™ integrated development environment (IDE) is part of the Vitis unified software platform. The Vitis IDE is designed to be used for the development of embedded software applications targeted towards Xilinx® embedded processors. The Vitis IDE works with hardware designs created with Vivado® Design Suite. The Vitis IDE is based on the Eclipse open source standard.
|Zynq UltraScale+MPSoC Software Developer Guide||UG1137|
This document provides the software-centric information required for designing and developing system software and applications for the Xilinx® Zynq® UltraScale+™ MPSoC devices.
|Zynq-7000 All Programmable SoC Software Developers Guide||UG821|
This document summarizes the software-centric information required for designing with Xilinx ® Zynq ® -7000 All Programmable SoC devices
Zynq Migration Guide - Zynq-7000 AP SoC to Zynq UltraScale+ MPSoC Devices
|UG1213||Summarizes the migration process from the Xilinx® Zynq®-7000 device to the Zynq UtlraScale+™ MPSoC device.|
Zynq-7000 All Programmable SoC - Technical Reference Manual
|UG585||Technical reference manual for the Zynq®-7000 All Programmable SoC.|
|ZYNQMP||Zynq UltraScale+ MPSoC TRM||UG1085||Describes the processing system in the Zynq® UltraScale+™ MPSoC including the Cortex®-A53 64-bit quad-core processor and Cortex-R5 dual-core realtime processor.|
A selection of Xilinx Answer Records are available on Xilinx Answer Record