Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. |
1 1) | PSBATT | 1.2 V ... 1.5 V | - | Battery connection. | Battery Power Domain usage. When not used, tie to GND. |
1 | 3.3VIN | 3.3 V (± 5 %) | - | Management power supply. | Management module power supply. 0.5 A recommended. |
GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.): |
1 1) | GT_DCDC | 3.3 V (± 5 %) 2) |
| GTH transceiver power supply. | Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. |
1 1) | EN_PLL_PWR | - | PD 3), GND | PLL power enable. |
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1 1) | PG_PLL_1V8 | - | PU 3), 3.3 V | PLL power good status. |
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2 | Processing System (PS): | Procedure for PS starting. |
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2.1 | Low-power domain: | Bring-up for low-power domain PS. |
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2.1.1 | LP_DCDC | 3.3 V (± 5 %) 2) | - | Low-power domain power supply. | Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution. |
2.1.2 | EN_LPD | - | PU 3), 3.3 V | Low-power domain power enable. |
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2.1.3 | LP_GOOD | - | PU 3), 3.3 V | Low-power domain power good status. | Module power-on sequencing for low-power domain finished. |
2.2 | Full-power domain: | Bring-up for full-power domain PS. | Full-power PS domain needs powered low-power PS domain. |
2.2.1 | DCDCIN | 3.3 V (± 5 %) 2) |
| Full-power domainand GTR transceiver power supply. | Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution. |
2.2.2 | EN_FPD | 3.3 V | - | Full-power domain power enable. |
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2.2.3 | PG_FPD | - | PU 3), 3.3 V | Full-power domain power good status. | Module power-on sequencing for full-power domain finished. |
2.2.4 | EN_DDR | 3.3 V | - | DDR memory power enable. |
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2.2.5 | PG_DDR |
| PU 3), 3.3 V | DDR memory power good status. | Module power-on sequencing for DDR memory finished. |
2.3 | GTR Transceiver | Procedure for GTR transceiver starting. | PS transceiver usage needs powered PS (low- and full-power domain). |
2.3.1 | EN_PSGT | 3.3 V | - | GTR transceiver power enable. |
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2.3.2 | PG_PSGT | - | PU 3), 3.3 V | GTR transceiver power good status. | Module power-on sequencing for GTR transceiver finished. |
2 | Programmable Logic (PL) | Procedure for PL starting. | PS and PL can be started independently. |
2.1 | PL_DCIN | 3.3 V (± 5 %) 2) 4) | - | Programmable logic power supply. | Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution. |
2.2 | EN_PL | - | PU 3), 3.3 V | Programmable logic power enable. |
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2.3 | PG_PL | - | PU 3), 3.3 V | Programmable logic power good status. | Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier. |
2.4 | VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 | 5) | - | Module bank voltages. | Enable bank voltages after PG_PL deassertion. |
2.5 | PG_VCU | - | PU 3), 3.3 V | VCU power good status. |
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3 | GTH / GTY Transceiver | Procedure for GTH / GTY transceiver starting. | PL transceiver usage needs powered PL and low-power PS domain. |
3.1 | GT_DCDC | 3.3 V (± 5 %) 2) | - | GTH transceiver power supply. | Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. |
3.2 | EN_GT_R | 3.3 V | - | GTH / GTY transceiver power enable. |
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3.3 | PG_GT_R | - | PU 3), 3.3 V | GTH / GTY transceiver power good status. |
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