Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0711+TRM for online version of this manual and the rest of available documentation.

Trenz Electronic TE0711 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, 32 MByte Quad SPI Flash memory for configuration and operation and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/O's are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoM's in 4 x 5 cm form factor are mechanically compatible.

Key Features

• Industrial-grade Xilinx Artix-7 (15T to 100T) FPGA, supported by the free Xilinx Vivado WebPACK tool

• Rugged for shock and high vibration

• FTDI FT2232H USB 2.0 high-speed to UART/FIFO

• 32 MByte QSPI Flash memory (with XiP support)

• 100 MHz MEMS oscillator

• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips

• 178 FPGA I/Os (84 differential pairs) are available on board-to-board connectors

• On-board high-efficiency DC-DC converters

  • 4.0 A x 1.0 V power rail

  • 1.0 A x 1.8 V power rail

  • 1.0 A x 1.5 V power rail

• System management and power sequencing

• eFUSE bit-stream encryption

• AES bit-stream encryption

• User LED

• Evenly-spread supply pins for good signal integrity

Assembly options for cost or performance optimization available upon request.

Block Diagram

Figure 1: TE0711-01 block diagram.

Main Components

Figure 2: TE0711-01 PCB.

1. Xilinx Artix-7 FPGA, U5
2. 4A PowerSoC DC-DC converter for 1.0V (Altera EN6347QI), U1
3. 1A PowerSoC DC-DC converter for 1.8V (Altera EN5311QI), U11
4. 32 MByte Quad SPI Flash memory 32 MByte Quad SPI Flash memory (Cypress S25FL256S), U7
5. Dual USB to UART/FIFO bridge (FTDI FT2232H), U6
6. Load switch for 3.3V voltage level (Texas Instruments TPS27082L), Q1
7. B2B connector Samtec Razor Beam™ LSHM-150, JM1
8. B2B connector Samtec Razor Beam™ LSHM-150, JM2
9. B2B connector Samtec Razor Beam™ LSHM-130, JM3
10. System Controller CPLD (Lattice Semiconductor LCMXO2-256HC), U4
11. 100.000000 MHz reference clock connected to the FPGA bank 14 (SiTime SiT8008), U8
12. 12.000000 MHz reference clock connected to the USB to UART/FIFO bridge (SiTime SiT8008), U3
    
13. Configuration data serial EEPROM for USB to UART/FIFO bridge (Microchip 93AA56), U2
    
14. Voltage detector for "Power OK" signalling (Texas Instruments TPS3805H3), U23

Initial Delivery State

Table 1: TE0711-01 initial delivery state.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the FPGA's I/O banks and B2B connector:

Table 2: Voltage ranges and pin-outs of available logic banks of the FPGA.

Refer to Master Pin-out Table as primary reference for the pin mapping information.

JTAG Interface

JTAG access to the Xilinx Artix-7 and to the System Controller CPLD is provided through B2B connector JM2.

Table 3: Pin mapping of JTAG Interface on B2B connector

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table 4: Pin description of System Controller CPLD.

On-board LEDs

The TE0711 SoM has total of 4 on-board LED's. LED's D1, D2 and D3 are connected to the Xilinx Artix-7 FPGA and can be freely used by user design. LED D4 is the System Controller CPLD status LED.

Table 5: Description of on-board LED's.

Clocking

The TE0711-01 is equipped with MEMS oscillator (SiT8008AI-73-XXS-100.000000E, U8) to provide 100 MHz clock signal for Xilinx Artix-7 FPGA pin P17.

On-board Peripherals

32 MByte Quad SPI Flash Memory

On-board SPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

System Controller CPLD

The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Low level at NRST_SC0 pin also resets the FPGA. This signal can be driven from the user’s PCB via the B2B connector pin JM2-18. Input EN_SC3 is also gated to FPGA Reset and should be open or pulled up for normal operation. EN_SC3 low turns off on board DC-DC converters and stops power-on sequencing.

It is possible for the user to create their own system controller design using the Lattice Diamond software. Once created the design can be programmed into the device using the JTAG pins. The signal JTAGSEL should be set to 3.3V to enable programming mode. For normal operation it should be set to 0V.

There are one status LED connected to the system controller CPLD. When the FPGA is not configured the LED will flash continuously. Finally once FPGA configuration has completed the LEDs can be used in the user's FPGA design.

Dual channel USB to UART/FIFO

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2A for system startup is recommended.

Table 6: Typical power consumption.

Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises).

Power-On Sequence

For highest efficiency of on board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets STAT_SC2 signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx Artix-7 datasheet DS181 for additional information. Also check related baseboard documentation when choosing baseboard design for TE0711-01 module.

A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply has stabilized. Than 3.3V supply will be available on the B2B connector pins.

The regulators can be powered from the 3.3V supply or a 5V supply if preferred. The options for powering the board are as follows:

• Apply 5V to pins VIN and 3.3V to pins 3.3VIN on the board connector
• Apply 3.3V to pins VIN and 3.3VIN on the board connectors.

Power Rails

Table 7: Power rails of SoM on B2B connectors.

Bank Voltages

Table 8: Range of FPGA's bank voltages.

See the Artix7 datasheet DS181 for the allowable voltage range.

Board to Board Connectors

Variants Currently In Production

Table 9: Differences between TE0711-01 module variants.

Technical Specifications

Absolute Maximum Ratings

Table 10: Absolute maximum ratings.

Recommended Operating Conditions

Table 11: Recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
• Mating height with standard connectors: 8mm
• PCB thickness: 1.6mm
• Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

Figure 3: Physical dimensions of the TE0711-01 board.

Weight

20.6 g Plain module.

8.8 g Set of nuts and bolts.

Revision History

Hardware Revision History

Table 12: Hardware revisions.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

Date	Revision	Contributors	Description
		John Hartfiel	Update Power Rail Section
2017-11-10	v.33	John Hartfiel	Replace B2B connector section
2017-01-29	v.30	Jan Kumann	New block diagram.
2017-01-01	v.10	Ali Naseri, Thorsten Trenz, Jan Kumann	TRM revision.
2015-06-05	v.1	Antti Lukats	Initial version.

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