This is preliminary based on Vivado 2015.4 release, the "DDR Less" flow should become even easier with the next Vivado releases. |
Step by Step
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0
#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
//Status = DDRInitCheck();
Create BOOT.BIN
Thats all, PS will load the FPGA bitstream and then do nothing.