Template Revision 2.2

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"

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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Create DrawIO object here: Attention if you copy from other page, use

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment

      • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

        • <type>_<main section>_<name>

          • type: Figure, Table
          • main section:
            • "OV" for Overview
            • "SIP" for Signal Interfaces and Pins,
            • "OBP" for On board Peripherals,
            • "PWR" for Power and Power-On Sequence,
            • "B2B" for Board to Board Connector,
            • "TS" for Technical Specification
            • "VCP" for Variants Currently in Production
            •  "RH" for Revision History
          • name: custom, some fix names, see below
        • Fix names:
          • "Figure_OV_BD" for Block Diagram

          • "Figure_OV_MC" for Main Components

          • "Table_OV_IDS" for Initial Delivery State

          • "Table_PWR_PC" for Power Consumption

          • "Figure_PWR_PD" for Power Distribution
          • "Figure_PWR_PS" for Power Sequence
          • "Figure_PWR_PM" for Power Monitoring
          • "Table_PWR_PR" for Power Rails
          • "Table_PWR_BV" for Bank Voltages
          • "Table_TS_AMR" for Absolute_Maximum_Ratings

          • "Table_TS_ROC" for Recommended_Operating_Conditions

          • "Figure_TS_PD" for Physical_Dimensions
          • "Table_VCP_SO" for TE_Shop_Overview
          • "Table_RH_HRH" for Hardware_Revision_History

          • "Table_RH_DCH" for Document_Change_History
      • Use Anchor in the document: add link macro and add "#<anchorname>
      • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
  • ...


Note for Download Link of the Scroll ignore macro:

Download PDF version of this document.

Table of Contents


Notes :

The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. TE0714 is the smallest module with transceiver (3 x 4 cm).

Refer to http://trenz.org/te0714-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • List of key features of the PCB

Different configurations for cost and performance optimization available upon request. Available options are:

Block Diagram

Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

  1. Xilinx Artix-7 FPGA (XC7A series), U4
  2. 16 MByte SPI Flash, U7
  3. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  4. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  5. 25 MHz oscillator, U8
  6. Single output low-dropout linear regulator (1.2V_MGT), U6
  7. Single output low-dropout linear regulator (1.0V_MGT), U5
  8. Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
  9. Red indication LED, D4
  10. Step-down DC-DC converter (1.0V), U1
  11. PFET load switch with configurable slew rate (3.3V), Q1
  12. Low-power step-down DC-DC converter (1.8V), U3
  13. Voltage detector for circuit initialization and timing supervision, U23 

Initial Delivery State

Storage device name



SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit


SPI Flash main array

demo design


Not programmed

eFUSE Security

Not programmed

Control Signals

  • Overview of Boot Mode, Reset, Enables,
Boot process is controlled by signals on the board to board (B2B) connector.


Signal State




high or open

Master SPI, x4 Mode

low or ground

Slave SelectMAP

PROG_Binputpulsed lowClear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONEoutputhighCompletion of configuration sequence.

SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.

Signals, Interfaces and Pins

Notes :

  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

JTAG Interface

JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1. 

Signal Name

B2B Pin



Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
14JM236VCCIO_0NB! 17 LVDS pairs possible.
15JM248VCCIO15Supplied by the baseboard.
34JM148VCCIO34Supplied by the baseboard.



4 x GTP lanes.

Please refer to the Pin-out  tables page for additional information. 

On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Quad SPI Flash

On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant.

On-board LED

There is one LED on TE0714 module.








User programmable



Default Frequency





25 MHz



Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.




Frequency depends on the module variant

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

TE0714 needs one single power supply with nominal of 3.3V.

Power Consumption

Test Condition (25 °C ambient)VIN Current mANotes
TE0714-35, TEBT0714, empty design, GT not enabled110mA

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.

Power Rails

Voltages on B2B-


B2B JM1-Pin

B2B JM2-Pin

VIN98, 100-inputsupply voltage
VCCIO_0-54inputhigh range bank voltage
VCCIO_15-53inputhigh range bank voltage
VCCIO_3462-inputhigh range bank voltage
3.3V84-outputinternal 3.3V voltage level
1.8V-17outputinternal 1.8V voltage level

Bank Voltages




0 Config and B14

1.8V or 3.3V

Depends on module assembly variant. See R21, R22 and R27 assembly option*



Supplied from baseboard via B2B connector, max 3.3V



Supplied from baseboard via B2B connector, max 3.3V
  • *R21 assembled: 3.3V and B2B is output if R27 is assembled
  • *R22 assembled 1.8V and B2B is output if R27 is assembled
  • *R21 and R22 not assembled , B2B is input and carrier defines voltage → pay attention on assembled flash!

Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsReference Document

VIN supply voltage




HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181

Voltage on module JTAG pins


VCCO_0 + 0.55


Xilinx datasheet DS181

Storage temperature





Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage3.1353.45V-
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.20VVXilinx datasheet DS181
Voltage on module JTAG pins0VCCO_0 + 5%VXilinx datasheet DS181

Physical Dimensions

All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.

Variants Currently In Production

Trenz shop TE0714 overview page
English pageGerman page

On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

Revision History

Hardware Revision History

DateRevisionPCNDocumentation LinkNote
2016-08-0402PCN-20160815TE0714-02VCCIO0 added to B2B




Hardware revision number is printed on the PCB board next to the module model number separated by the dash.


Document Change History





  • VCCIO_0 voltages and connection

2019-03-04v55John Hartfiel
  • Restore and modify v.50
  • Correction max IO count on key features
  • Change history table
  • typo correction
2019-01-07v.50John Hartfiel
  • Updated to TRM version 2.2
  • Style modifications


v.48Martin Rohrmüller
  • Updated to TRM version 2.1
  • Updated B2B Connectors
  • Style modifications


Martin Rohrmüller
  • Added power rail section
  • Added Rev 02 Flash PCN
  • Corrected table headings
2018-09-17v.36Martin Rohrmüller
  • Update to TRM version 2.0 with DrawIO Figures

  • Added Figure Power Distribution


Martin RohrmüllerCorrected clock net designator in table.


Jan Kumann
  • Board-to-Board I/O section added.
  • New physical dimensions images.
  • Documents sections rearranged.


John Hartfiel
  • Notes on Clocking section.
2017-01-27v.25Jan Kumann
  • New block diagram.


Jan Kumann
  • Changes in the document structure, few corrections.

Thorsten Trenz, Emmanuel Vassilakis

  • Hardware revision 02 specific changes.



Antti Lukats

  • Initial version.