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Table of Contents


The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC (XC7Z035, XC7Z045 or XC7Z100).

These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are available in several versions.

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

Use short link the Wiki Ressource page: for example:
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Refer to http://trenz.org/te0782-info for the current online version of this manual and other available documentation.

Key Features

Assembly options for cost or performance optimization available upon request.

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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IMPORTANT NOTE: In case of copy and paste the TRM skeleton to a new Wiki page, delete the Draw.IO diagrams and the PNGs, otherwise due to the linkage of the copied diagrams every change in the TRM Skeleton will effect also in the created TRM and vice versa!

See page "Diagram Drawing Guidelines" how to clone an existing diagram as suitable template for the new diagram! 


Main Components

  1. Xilinx Zynq-7000 SoC, U1
  2. Lattice Semiconductor MachXO2 1200HC CPLD, U14
  3. 4Gbit DDR3L SDRAM, U19
  4. 4Gbit DDR3L SDRAM, U10
  5. I²C voltage translator, U25
  6. Intersil ISL12020MIRZ Real Time Clock, U17
  7. Microchip USB3320C USB PHY transceiver, U4
  8. Microchip USB3320C USB PHY transceiver, U8
  9. SiTime SiT8008 52.000000 MHz oscillator, U7
  10. 32 MByte QSPI Flash memory, U38
  11. SiTime SiT8008 33.333333 MHz oscillator, U61
  12. SI5338A programmable quad PLL clock generator, U2
  13. SiTime SiT8008 25.000000 MHz oscillator, U3
  14. TPS74801 LDO @1.5V, U23
  15. LT quad 4A PowerSoC DC-DC converter (@1.0V), U13
  16. LT quad 4A PowerSoC DC-DC converter (@3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT), U16
  17. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
  18. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3
  19. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
  20. Marvell Alaska 88E1512 Gigabit Ethernet PHY, 20
  21. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
  22. Micron Technology 4 GByte eMMC, U15
  23. Microchip 128Kbit I²C EEPROM, U26
  24. Microchip 2Kbit I²C MAC EEPROM, U24
  25. Microchip 2Kbit I²C MAC EEPROM, U22
  26. TPS51206 DDR reference voltage and termination regulator, U6
  27. TPS799 LDO @1.8V_MGT, U5
  28. SiTime SiT8008 25.000000 MHz oscillator, U11

Initial Delivery State

Storage device nameContentNotes
24LC128-I/ST not programmedUser content

24AA025E48 EEPROM's

User content not programmed

Valid MAC Address from manufacturer
Si5338A OTP Areanot programmed-
eMMC Flash MemoryEmpty, not programmedExcept serial number programmed by flash vendor

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit



SPI Flash main array

demo design

HyperFlash Memorynot programmed-


Not programmed


eFUSE Security

Not programmed


Table 1: Initial delivery state of programmable devices on the module

Boot Process

4 of the 7 boot mode strapping pins (MIO2 ... MIO8) of the Xilinx Zynq-7000 SoC device are hardware programmed on the board, 3 of them are set by the SC CPLD firmware. The boot strapping pins are evaluated by the Zynq device soon after the 'PS_POR' signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0782 board is programmed in the SC CPLD firmware to boot initially from the on-board QSPI Flash memory U38. See section Bootmode in the TE0782 SC CPLD reference Wiki page.

The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq-7000 device.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq-7000 SoC's I/O banks signals connected to the B2B connectors:


B2B Connector

I/O Signal Count








Max voltage 3.3V







Max voltage 3.3V






Max voltage 3.3V







Max voltage 3.3V







Max voltage 1.8V
34HPJ14220UserMax voltage 1.8V

Table 2: General overview of board to board I/O signals

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq-7000 SoC used on the TE0782 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Board to

BankTypeLaneSignal NameB2B PinFPGA Pin
  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N
  • J3-32
  • J3-30
  • J3-31
  • J3-29
  • MGTXRXP0_109
  • MGTXRXN0_109
  • MGTXTXP0_109
  • MGTXTXN0_109
  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N
  • J3-28
  • J3-26
  • J3-27
  • J3-25
  • MGTXRXP1_109
  • MGTXRXN1_109
  • MGTXTXP1_109
  • MGTXTXN1_109
  • MGT_RX2_P
  • MGT_RX2_N
  • MGT_TX2_P
  • MGT_TX2_N
  • J3-24
  • J3-22
  • J3-23
  • J3-21
  • MGTXRXP2_109
  • MGTXRXN2_109
  • MGTXTXP2_109
  • MGTXTXN2_109
  • MGT_RX3_P
  • MGT_RX3_N
  • MGT_TX3_P
  • MGT_TX3_N
  • J3-20
  • J3-18
  • J3-19
  • J3-17
  • MGTXRXP3_109
  • MGTXRXN3_109
  • MGTXTXP3_109
  • MGTXTXN3_109
  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N
  • J3-16
  • J3-14
  • J3-15
  • J3-13
  • MGTXRXP0_110
  • MGTXRXN0_110
  • MGTXTXP0_110
  • MGTXTXN0_110
  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N
  • J3-12
  • J3-10
  • J3-11
  • J3-9
  • MGTXRXP1_110
  • MGTXRXN1_110
  • MGTXTXP1_110
  • MGTXTXN1_110
  • MGT_RX6_P
  • MGT_RX6_N
  • MGT_TX6_P
  • MGT_TX6_N
  • J3-8
  • J3-6
  • J3-7
  • J3-5
  • MGTXRXP2_110
  • MGTXRXN2_110
  • MGTXTXP2_110
  • MGTXTXN2_110
  • MGT_RX7_P
  • MGT_RX7_N
  • MGT_TX7_P
  • MGT_TX7_N
  • J3-4
  • J3-2
  • J3-3
  • J3-1
  • MGTXRXP3_110
  • MGTXRXN3_110
  • MGTXTXP3_110
  • MGTXTXN3_110
  • MGT_RX8_P
  • MGT_RX8_N
  • MGT_TX8_P
  • MGT_TX8_N
  • J1-1
  • J1-3
  • J1-2
  • J1-4
  • MGTXRXP0_111
  • MGTXRXN0_111
  • MGTXTXP0_111
  • MGTXTXN0_111
  • MGT_RX9_P
  • MGT_RX9_N
  • MGT_TX9_P
  • MGT_TX9_N
  • J1-5
  • J1-7
  • J1-6
  • J1-8
  • MGTXRXP1_111
  • MGTXRXN1_111
  • MGTXTXP1_111
  • MGTXTXN1_111
  • MGT_RX10_P
  • MGT_RX10_N
  • MGT_TX10_P
  • MGT_TX10_N
  • J1-9
  • J1-11
  • J1-10
  • J1-12
  • MGTXRXP2_111
  • MGTXRXN2_111
  • MGTXTXP2_111
  • MGTXTXN2_111
  • MGT_RX11_P
  • MGT_RX11_N
  • MGT_TX11_P
  • MGT_TX11_N
  • J1-13
  • J1-15
  • J1-14
  • J1-16
  • MGTXRXP3_111
  • MGTXRXN3_111
  • MGTXTXP3_111
  • MGTXTXN3_111
  • MGT_RX12_P
  • MGT_RX12_N
  • MGT_TX12_P
  • MGT_TX12_N
  • J1-17
  • J1-19
  • J1-18
  • J1-20
  • MGTXRXP0_112
  • MGTXRXN0_112
  • MGTXTXP0_112
  • MGTXTXN0_112
  • MGT_RX13_P
  • MGT_RX13_N
  • MGT_TX13_P
  • MGT_TX13_N
  • J1-21
  • J1-23
  • J1-22
  • J1-24
  • MGTXRXP1_112
  • MGTXRXN1_112
  • MGTXTXP1_112
  • MGTXTXN1_112
  • MGT_RX14_P
  • MGT_RX14_N
  • MGT_TX14_P
  • MGT_TX14_N
  • J1-25
  • J1-27
  • J1-26
  • J1-28
  • MGTXRXP2_112
  • MGTXRXN2_112
  • MGTXTXP2_112
  • MGTXTXN2_112
  • MGT_RX15_P
  • MGT_RX15_N
  • MGT_TX15_P
  • MGT_TX15_N
  • J1-29
  • J1-31
  • J1-30
  • J1-32
  • MGTXRXP3_112
  • MGTXRXN3_112
  • MGTXTXP3_112
  • MGTXTXN3_112

Table 3: MGT lanes

There are 2 clock sources for the GTX transceivers. MGT_CLK1 and MGT_CLK4 are connected directly to B2B connector J3 and J1, so the clock can be provided by the carrier board. Clocks MGT_CLK0, MGT_CLK3, MGT_CLK5 and MGT_CLK6 are provided by the on-board clock generator (U2). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

BankTypeClock signalSourceFPGA PinNotes
109GTXMGT_CLK3_PU2, CLK3AMGTREFCLK1P_109, AF10Supplied by on-board Si5338A
110GTXMGT_CLK0_PU2, CLK2AMGTREFCLK0P_110, AA8Supplied by on-board Si5338A
MGT_CLK1_NJ3-39MGTREFCLK1P_110, AC8Supplied by B2B connector J3
111GTXMGT_CLK4_NJ1-40MGTREFCLK0P_111, U8Supplied by B2B connector J1
MGT_CLK5_PU2, CLK1AMGTREFCLK1P_111, W8Supplied by on-board Si5338A
112GTXMGT_CLK6_PU2, CLK0AMGTREFCLK0P_112, N8Supplied by on-board Si5338A

Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector J3.

JTAG Signal

B2B Connector Pin


Table 5: Zynq JTAG interface signals

JTAG access to the LCMXO2-1200HC System Controller CPLD U14 is provided through B2B connector J3.

JTAG Signal

B2B Connector Pin


Table 6: System Controller CPLD JTAG interface signals

Pin J3-136 'JTAGENB' of B2B connector J3 is used to access the JTAG interface of the SC CPLD. Set high to program the System Controller CPLD via JTAG interaface.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameDirectionFunctionDefault Configuration
BOOTMODEininsignal forwarded to MIO9 and currently used as UART RX line
CONFIGXinoutsignal forwarded to MIO8 and currently used as UART TX line
RESINinnRESETexternal Board Reset
M_TDOoutCPLD JTAG interface

JTAGENBinenable JTAGpull high for programming SC CPLD firmware
I2C_SCLin / outI²C data lineI²C bus of board

I2C_SDAinI²C clock
CPLD_IOin / outuser GPIOcurrently not used
ETH1_RESEToutreset GbE PHY U18see current SC CPLD firmware
OTG-RSToutreset USB2 PHYs
U4 and U8
see current SC CPLD firmware
RTC_INTininterruptinterrupt from RTC
PS_SRSToutZynq control signal

reset PS of Zynq-7000 SoC
DONEinPL configuration completed
PROG_BoutPL configuration reset signal
INITinLow active FPGA initialization pin or configuration error signal
PS_PORoutPS power-on reset

Bootmode Pins

currently configured in SC CPLD firmare to boot from QSPI Flash

MIO8inuser MIO pins

currently used as UART interface
MMC_RSToutReset MMC Flashsee current SC CPLD firmware
ETH1-RESET33inreset GbE PHY U18reset signal from Zynq-7000 level shifted to 1.8V

reset USB2 PHYs
U4 and U8

reset signal from Zynq-7000 level shifted to 1.8V
LED1 ... LED2outLED status signalsee current CPLD firmware
CPLD_GPIO0 ... CPLD_GPIO5in / outuser GPIOcurrently not used
EN_1VoutPower control

enable signal DCDC U13 '1V'
PG_1Vinpower good signal DCDC U13 '1V'
EN_1.0V_MGToutenable signal DCDC U16 '1.0V_MGT'
PG_1.0V_MGTinpower good signal DCDC U16 '1.0V_MGT'
EN_1.2V_MGToutenable signal DCDC U16 '1.2V_MGT'
PG_1.2V_MGTinpower good DCDC U16 '1.2V_MGT'
EN_1.8Voutenable signal DCDC U16 '1.8V'
PG_1.8Vinpower good signal DCDC U16 '1.8V'
EN_3.3Voutenable signal DCDC U16 '3.3V'
PG_3.3Vinpower good signal DCDC U16 '3.3V'
PG_1V5inpower good signal DCDC U23 '1.5V'

Table 7: System Controller CPLD special purpose pins.

See also TE0782 CPLD reference Wiki page.

Default PS MIO Mapping

MIOFunctionConnected to
0USB2 PHYs ResetSC CPLD (used as level translator)
7Ethernet PHY1 ResetSC CPLD (used level translator)
8UART TXoutput, muxed to B2B by the SC CPLD
9UART RXinput, muxed to B2B by the SC CPLD
16..27ETH0Ethernet RGMII PHY

Table 8: Zynq PS MIO mapping

Gigabit Ethernet

The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11), the 125MHz output clock of both PHYs are connected to Zynq's PL bank 35.

ETH1 PHY connection:

PHY PINZynq PS / PLSystem Controller CPLDNotes
LED0Bank 35, Pin B12--
LED1Bank 35, Pin C12--
InterruptBank 35, Pin A15--
CONFIGBank 35, Pin F14-When pin connected to GND, PHY Address is strapped to 0x00 by default
MDI--on B2B J2 connector

Table 9: General overview of the Gigabit Ethernet1 PHY signals

ETH2 PHY connection:

PHY PINZynq PS / PLSystem Controller CPLDNotes
MDC/MDIOBank 35, Pin C17/B17--
LED0Bank 35, Pin K15--
LED1Bank 35, Pin B16--
InterruptBank 35, Pin A17--
CONFIGBank 35, Pin E15-When pin connected to GND, PHY Address is strapped to 0x00 by default
RESETnBank 35, Pin B15--
RGMIIBank 9--


on B2B J2 connector

Table 10: General overview of the Gigabit Ethernet2 PHY signals

USB Interface

The TE0782 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).

USB0 PHY connection:

PHY PinZynq PS / PLCPLDB2B Connector J2Notes
ULPIMIO28..39--Zynq USB0 MIO pins are connected to the PHY
REFCLK---52MHz from on board oscillator (U7)
REFSEL[0..2]---000 GND, select 52MHz reference Clock
CLKOUTMIO36--Connected to 1.8V selects reference clock operation mode
DP,DM--USB1_D_P, USB1_D_NUSB Data lines
CPEN--VBUS1_V_ENExternal USB power switch active high enable signal
VBUS--USB1_VBUSConnect to USB VBUS via a series resistor. Check reference schematic.
ID--OTG1_IDFor an A-Device connect to ground, for a B-Device left floating

Table 11: General overview of the USB0 PHY signals

USB1 PHY connection:

PHY PinZynq PS / PLCPLDB2B Connector J2Notes
ULPIMIO40..51--Zynq USB1 MIO pins are connected to the PHY
REFCLK---52MHz from on board oscillator (U7)
REFSEL[0..2]---000 GND, select 52MHz reference Clock
CLKOUTMIO48--Connected to 1.8V selects reference clock operation mode
DP,DM--USB2_D_P, USB2_D_NUSB Data lines
CPEN--VBUS2_V_ENExternal USB power switch active high enable signal
VBUS--USB2_VBUSConnect to USB VBUS via a series resistor. Check reference schematic.
ID--OTG2_IDFor an A-Device connect to ground, for a B-Device left floating

Table 12: General overview of the USB1 PHY signals

I2C Interface

The on-board I2C components are connected to bank 35 pins L15 (I2C_SDA) and L14 (I2C_SCL).

I2C addresses for on-board components:

EEPROM24LC128-I/STU260x53user data
EEPROM24AA025E48T-I/OTU220x50MAC address EEPROM
EEPROM24AA025E48T-I/OTU240x51MAC address EEPROM
RTCISL12020MIRZU170x6FTemperature compensated real time clock
Battery backed RAMISL12020MIRZU170x57Integrated in RTC
SC CPLDLCMXO2-1200HC-4TG100IU14user-

Table 13: Address table of the I2C bus slave devices

Pin Definitions

Pins with names ending with _VRN and _VRP are connected to Zynq PL HP bank special purpose pins VRN/VRP and can be routed to DCI calibration resistors on the baseboard. Otherwise they are usable as general purpose I/Os.

Bank 35 has 100 ohm DCI calibration resistors installed, it is also possible to "borrow" the DCI calibration from bank 35 for banks 34 and 33. For more detailed information about the DCI check Xilinx documentation.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U14) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0782 CPLD reference Wiki page.

eMMC Flash Memory

eMMC Flash memory device (U15) is connected to the Zynq PS MIO bank 500 pins MIO10..MIO15. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

DDR3L Memory

By default TE0782-02 module has two 16-bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) chips (U10, U19) arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM.

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash memory for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 (U38) with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet PHYs

On-board Gigabit Ethernet PHYs (U18, U20) are provided by Marvell Alaska 88E1512. The Ethernet PHYs' RGMII interfaces are connected to the Zynq's PS MIO bank 501 and to PL bank 9. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of both PHYs is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB ULPI PHYs

Hi-speed USB ULPI PHYs (U4. U8) are provided with USB3320 from Microchip. The ULPI interfaces are connected to the Zynq PS USB0 and USB1 via MIO28..51, bank 501 (see also section USB interface). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U7).


Two Microchip 24AA025E48 serial EEPROMs (U22, U24) contain globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The devices are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROMS areaccessible over I2C bus (see also section I²C interface).

Configuration EEPROM

The TE0782 board contains one EEPROM (U26) for configuration and general user purposes. The EEPROMs is provided by Microchip 24LC128-I/ST with 128 KBit memory density, the EEPROM is areaccessible over I2C bus (see also section I²C interface).

Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator Si5338A (U2) chip on-board. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator (U3) is connected to the pin IN3 and is used to generate the output clocks. The output voltage of the oscillator is provided by the 1.8V power rail, thus making output frequency available as soon as 1.8V is present. All 4 of the Si5338 clock outputs are connected to the MGT banks of the Zynq device. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.


External clock signal supply from B2B connector J3, pins J3-38 / J3-40


25.000000 MHz

Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U3)

IN4-LSB of the default I2C address, wired to ground mean address is 0x70



Not connected



Wired to ground


reference clock 0 of Bank 112 GTX



reference clock 1 of Bank 111 GTX



reference clock 0 of Bank 110 GTX

CLK3 A/B-reference clock 1 of Bank 109 GTX

Table 14: General overview of the on-board quad clock generator I/O signals


The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008AI oscillator, U61PS_CLK33.333333 MHzZynq SoC U1, pin A22
SiTime SiT8008BI oscillator, U21-25.000000 MHzQuad PLL clock generator U2, pin 3
SiTime SiT8008AI oscillator, U7-52.000000 MHzUSB2 PHYs U4 and U8, pin 26
SiTime SiT8008BI oscillator, U11-25.000000 MHzGbE PHYs U18 and U20, pin 34

Table 15: Reference clock signals

On-board LEDs

LEDColorConnected toDescription and Notes
D1RedSystem Controller CPLD U14, bank 3Exact function is defined by SC CPLD firmware
D2GreenSystem Controller CPLD U14, bank 3

Table 16: On-board LEDs

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 4A for system startup is recommended.

Power Consumption

Power InputTypical Current

Table 17: Power consumption

 * TBD - To Be Determined soon with reference design setup.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any Zynq's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

The Trenz TE0782 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

The power supply voltage 'C3.3V' of System Controller CPLD of the SoM have to be externally supplied with 3.3V nominal.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0782 module.

Power-On Sequence

Power-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

Power Rails

Power Rail Name on B2B ConnectorJ1 PinsJ2 PinsJ3 PinsDirectionNotes
VIN-165, 166, 167, 168-Inputexternal power supply voltage
C3.3V-147, 148-Inputexternal 3.3V power supply voltage

111, 112, 123, 124, 135 136

169, 170, 171, 172

-Outputinternal 3.3V voltage level
1.8V169, 170, 171, 172--Outputinternal 1.8V voltage level
VCCIO_10--99, 100Inputhigh range I/O bank voltage
VCCIO_11--159, 160Inputhigh range I/O bank voltage
VCCIO_12-159, 160-Inputhigh range I/O bank voltage
VCCIO_13-99, 100-Inputhigh range I/O bank voltage
VCCIO_3399, 100--Inputhigh performance I/O bank voltage
VCCIO_34159, 160--Inputhigh performance I/O bank voltage
VBAT_IN--124Inputbackup battery voltage

Table 18: Module power rails

Bank Voltages

BankSchematic NameVoltageRangeNotes
0-3.3 V-FPGA configuration
502-1.5 V-DDR3-RAM port
109 / 110 / 111 / 112-1.2 V-MGT
500 / 501-3.3 V-MIO banks
9 (HR)-1.8 V1.2V to 3.3VETH2 RGMII
10 (HR)VCCIO_10user1.2V to 3.3V-
11 (HR)VCCIO_11user1.2V to 3.3V-
12 (HR)VCCIO_12user1.2V to 3.3V-
13 (HR)VCCIO_13user1.2V to 3.3V-
33 (HP)VCCIO_33user1.2V to 1.8V-
34 (HP)VCCIO_34user1.2V to 1.8V-
35 (HP)-1.8 V1.2V to 1.8VHyper-RAM, Ethernet, I²C

Table 19: Module I/O bank voltages

See Xilinx Zynq-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

Variants Currently In Production

Trenz shop TE0782 overview page
English pageGerman page

Technical Specifications

Absolute Maximum Ratings





VIN supply voltage




LTM4644 datasheet
C3.3V supply voltage-0.33.6VLTM4644 datasheet
VBAT supply voltage-0.36VTPS780180 datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.6VXilinx document DS191
PS I/O input voltage-0.4VCCO_PSIO + 0.55VXilinx document DS191
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS191
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS191
HR I/O bank supply voltage, VCCO-0.53.6VXilinx document DS191
HR I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS191
Reference Voltage pin-0.52VXilinx document DS191
Differential input voltage-0.42.625VXilinx document DS191
MGT reference clocks absolute input voltage-0.51.32VXilinx document DS191
MGT absolute input voltage-0.51.26VXilinx document DS191

Voltage on SC CPLD pins




Lattice Semiconductor MachXO2 datasheet

Storage temperature




See eMMC MTFC4GMVEA datasheet

Table 20: Module absolute maximum ratings

Recommended Operating Conditions

VIN supply voltage11.412.6VLTM4644 datasheet, 12V nominal
C3.3V supply voltage3.33.465VLCMXO2-256HC, LTM4644 datasheet
VBAT supply voltage2.25.5VTPS780180 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS191
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS191
HP I/O banks supply voltage, VCCO1.141.89VXilinx document DS191
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS191
HR I/O banks supply voltage, VCCO1.143.465VXilinx document DS191
HR I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS191
Differential input voltage-0.22.625VXilinx document DS191
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range-4085°CXilinx document DS191, industrial grade Zynq temperarure range

Table 21: Recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

See Xilinx datasheet DS191 for more information about absolute maximum and recommended operating ratings for the Zynq-7000 chips.

Physical Dimensions

All dimensions are shown in millimeters.

Revision History

Hardware Revision History



PCN LinkDocumentation Link
-02current available board revision-TE0782-02
2015-05-2701Prototype only--

Table 22: Hardware revision history table

Document Change History

Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.


  • small corrections
  • linked B2B
2018-07-20v.33John Hartfiel
  • small style update


v.32Ali Naseri
  • Update TRM to new format and style

Ali Naseri
  • corrected minimum recommended VBAT supply voltage


Ali Naseri
  • updated Power section, added diagramms


Jan Kumann
  • Minor formatting

Jan Kumann
  • New block diagram
  • New product images
  • New physical dimensions drawing


Ali Naseri
  • New numbered pictures describing main components
  • Added variants in production
2016-06-27v.10Ali Naseri, Jan Kumann
  • Initial release

  • --