This is one of the easiest solutions to implement full multiboot application for any Xilinx 7 Series or Ultrascale FPGA.
A Microblaze based system should be made with following IP Core from Xilinx free Vivado IP Catalog:
Offset | Size | Content | Notes |
---|---|---|---|
Application bitstream #2 | |||
Application bitstream #2 | |||
Sizeof(u-boot.SREC) + padding | u-boot converted to SREC format | ||
0 + Sizeof(golden.bit) + padding | 0x2000 | u-boot flash environment | Offset must be larger than size of FPGA bitstream |
0x000000 | GOLDEN bitstream | First bootloader (like SREC SPI Loader) is embedded in BRAM and loaded with the bitstream |
Xilinx SREC SPI loader is used to bootstrap u-boot into external memory, then u-boot is used for all flash operations as required. The image to be written can be loaded to external RAM and then written to SPI Flash as needed.
Step by Step
This process involves least amount of custom coding, the only custom code is small function that talks to HWICAP, and the "check" of update mode in the SREC Loader. All functions related to SPI Flash erasing and writing are done with u-boot.
List of references source for additional information