Table of Contents |
On https://wiki.trenz-electronic.de/display/PD/TE0782-02+TRM the online version of this manual and other documents can be found. |
The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC. It is equipped with a Xilinx Zynq-7 (XC7Z035, XC7Z045 or XC7Z100).
These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are available in several versions.
All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Contact us for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.
This SoM has following peripherals on board:
Assembly options for cost or performance optimization available upon request.
Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782
Name | Note |
---|---|
BOOTMODE | user configurable (CPLD) |
CONFIGX | user configurable (CPLD) |
JTAGENB | JTAG operation |
RESIN | System-reset |
CLPD_GPIO0 | user GPIO |
CLPD_GPIO1 | user GPIO |
CLPD_GPIO2 | user GPIO |
CLPD_GPIO3 | user GPIO |
CLPD_GPIO4 | user GPIO |
CLPD_GPIO5 | user GPIO |
TE0782 supports primary boot from
Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).
JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.
Signal | B2B Pin |
---|---|
TCK | J3: 141 |
TDI | J3: 147 |
TDO | J3: 148 |
TMS | J3: 1142 |
CPLD-JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.
Signal | B2B Pin |
---|---|
M_TCK | J3: 81 |
M_TDI | J3: 87 |
M_TDO | J3: 82 |
M_TMS | J3: 88 |
JTAGENB pin in J3 should be kept low or grounded for normal operation. |
Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 MHz | U61 | PS_CLK | PS Subsystem main clock |
10/100/1000 Mbps ETH PHYs reference | 25 MHz | U11 | - | |
USB PHY reference | 52 MHz | U7 | - | |
PLL reference | 25 MHz | U3 | - | |
GT REFCLK1 | - | B2B connector | AC7/AC8 | Externally supplied from base |
GT REFCLK4 | - | B2B connector | U7/U8 | Externally supplied from base |
quad programmable clock (I2C) SI5338A | user | U2 | - | GT REFCLK0 GT REFCLK3 GT REFCLK5 GT REFCLK6 |
Peripheral | IC | Designator | PS | MIO | Notes |
---|---|---|---|---|---|
QSPI Flash | S25FL256SAGBHI20 | U38 | QSPI0 | MIO1...MIO6 | - |
Ethernet0 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U18 | ETH0; GPIO BANK35 | MIO16...MIO27, MIO52, MIO53 | - |
Ethernet0 10/100/1000 Mbps PHY Reset | GPIO | MIO7 | ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET | ||
Ethernet1 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U20 | GPIO BANK9, BANK35 | - | - |
Ethernet1 10/100/1000 Mbps PHY Reset | GPIO BANK35, Pin B15 | - | - | ||
USB0 | USB3320C-EZK | U4 | USB0 | MIO28...MIO39 | - |
USB0 Reset | GPIO | MIO0 | OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET | ||
USB1 | USB3320C-EZK | U8 | USB1 | MIO40...MIO51 | - |
USB1 Reset | GPIO | MIO0 | OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET | ||
Clock PLL | Si5338 | U2 | I2C | BANK35, Pin L14/L15 | Low jitter phase locked loop |
e-MMC (embedded e-MMC) | MTFC4GMVEA-4M IT | U15 | SDIO0 | MIO10...MIO15 | - |
HyperFlash RAM | S26KS512SDPBHI00x | U9 | GPIO BANK35 | - | optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) optional 2 x 32 MByte HyperFLASH |
HyperFlash RAM | S26KS512SDPBHI00x | U12 | GPIO BANK35 | - | as above |
EEPROM I2C | 24LC128-I/ST | U26 | GPIO BANK35, Pin L14/L15 | - | - |
EEPROM I2C | 24AA025E48T-I/OT | U22 | GPIO BANK35, Pin L14/L15 | - | MAC Address |
EEPROM I2C | 24AA025E48T-I/OT | U24 | GPIO BANK35, Pin L14/L15 | - | MAC Address |
RTC | ISL12020MIRZ | U17 | GPIO BANK35, Pin L14/L15 | - | Temperature compensated real time clock |
RTC Interrupt | ISL12020MIRZ | U17 | - | - | RTC_INT -> CPLD |
MIO | Configured as | B2B | Notes |
---|---|---|---|
0 | OTG-RST33 | - | connected to CPLD |
1 | QSPI0 | - | SPI Flash-CS |
2 | QSPI0 | - | SPI Flash-DQ0 |
3 | QSPI0 | - | SPI Flash-DQ1 |
4 | QSPI0 | - | SPI Flash-DQ2 |
5 | QSPI0 | - | SPI Flash-DQ3 |
6 | QSPI0 | - | SPI Flash-SCK |
7 | ETH1_RESET33 | - | connected to CPLD |
8 | GPIO | - | connected to CPLD and Pull-Up 3.3V |
9 | GPIO | - | connected to CPLD |
10 | MMC-D0 | - | - |
11 | MMC-CMD | - | - |
12 | MMC-CCLK | - | - |
13 | MMC-D1 | - | - |
14 | MMC-D2 | - | - |
15 | MMC-D3 | - | - |
16..27 | ETH0 | - | Ethernet RGMII PHY |
28..39 | USB0 | - | USB0 ULPI PHY |
40...51 | USB1 | - | USB1 ULPI PHY |
52 | ETH0 MDC | - | - |
53 | ETH0 MDIO | - | - |
The on-board I2C components are connected to BANK35, Pin L15 (I2C_SDA) and to BANK35, Pin L14 (I2C_SCL).
Device | IC | Designator | I2C-Address | Notes |
---|---|---|---|---|
EEPROM | 24LC128-I/ST | U26 | 0x53 | user data, parameter |
EEPROM | 24AA025E48T-I/OT | U22 | 0x50 | MAC Address |
EEPROM | 24AA025E48T-I/OT | U24 | 0x51 | MAC Address |
RTC | ISL12020MIRZ | U17 | 0x6F | Temperature compensated real time clock |
Battery backed RAM | ISL12020MIRZ | U17 | 0x57 | integrated in RTC |
PLL | SI5338A-B-GMR | U2 | 0x70 | Quad reference clock for GTX transceiver lanes |
CPLD | LCMXO2-1200HC-4TG100I | U14 | user | - |
Bank | Type | B2B | IO count | IO Voltage | Notes |
---|---|---|---|---|---|
10 | HR | J3 | 44 | user | 22 LVDS-pairs possible |
11 | HR | J3 | 40 | user | 20 LVDS-pairs possible |
12 | HR | J2 | 40 | user | 20 LVDS-pairs possible |
13 | HR | J2 | 40 | user | 20 LVDS-pairs possible |
33 | HR | J1 | 48 | user | 23 LVDS-pairs possible |
34 | HR | J1 | 42 | user | 20 LVDS-pairs possible |
For detailed information about the pin out, please refer to the Master Pinout Table.
D1 - Onboard RED LED
1 | Power problem |
2 | MGT Power problem |
3 | Reset from mainboard |
4 | FPGA not programmed |
This function depend on the CPLD revision.
D2 - Onboard GREEN LED
Green LED connected to MIO8
The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11).
ETH1 PHY connection:
PHY PIN | ZYNQ PS | System Controller CPLD | Notes |
---|---|---|---|
MDC/MDIO | MIO52, MIO53 | - | - |
LED0 | BANK35, Pin B12 | - | - |
LED1 | BANK35, Pin C12 | - | - |
Interrupt | BANK35, Pin A15 | - | - |
CONFIG | BANK35, Pin F14 | - | - |
RESETn | - | Pin 53 | ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET |
RGMII | MIO16..MIO27 | - | |
MDI | - | - | on B2B J2 connector |
ETH2 PHY connection:
PHY PIN | ZYNQ PS | System Controller CPLD | Notes |
---|---|---|---|
MDC/MDIO | BANK35, Pin C17/B17 | - | - |
LED0 | BANK35, Pin K15 | - | - |
LED1 | BANK35, Pin B16 | - | - |
Interrupt | BANK35, Pin A17 | - | - |
CONFIG | BANK35, Pin E15 | - | Pin connected to GND, PHY Address is strapped to 0x00 by default |
RESETn | BANK35, Pin B15 | - | - |
RGMII | BANK9 | - | - |
MDI | - | - | on B2B J2 connector |
The TE0782 is equipped with two USB PHYs USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.
The reference clock input of both PHYs is supplied from an on board 52MHz oscillator (U7).
USB0 PHY connection:
PHY Pin | Zynq Pin | CPLD | B2B Name (J2) | Notes |
---|---|---|---|---|
ULPI | MIO28..39 | - | - | Zynq USB0 MIO pins are connected to the PHY |
REFCLK | - | - | - | 52MHz from on board oscillator (U7) |
REFSEL[0..2] | - | - | - | 000 GND, select 52MHz reference Clock |
RESETB | MIO0 | OTG_RESET33 | - | OTG_RESET33 -> CPLD -> OTG_RESET |
CLKOUT | MIO36 | - | - | Connected to 1.8V selects reference clock operation mode |
DP,DM | - | - | USB1_D_P, USB1_D_N | USB Data lines |
CPEN | - | - | VBUS1_V_EN | External USB power switch active high enable signal |
VBUS | - | - | USB1_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
ID | - | - | OTG1_ID | For an A-Device connect to ground, for a B-Device left floating |
USB1 PHY connection:
PHY Pin | Zynq Pin | CPLD | B2B Name (J2) | Notes |
---|---|---|---|---|
ULPI | MIO40..51 | - | - | Zynq USB1 MIO pins are connected to the PHY |
REFCLK | - | - | - | 52MHz from on board oscillator (U7) |
REFSEL[0..2] | - | - | - | 000 GND, select 52MHz reference Clock |
RESETB | MIO0 | OTG_RESET33 | - | OTG_RESET33 -> CPLD -> OTG_RESET |
CLKOUT | MIO48 | - | - | Connected to 1.8V selects reference clock operation mode |
DP,DM | - | - | USB2_D_P, USB2_D_N | USB Data lines |
CPEN | - | - | VBUS2_V_EN | External USB power switch active high enable signal |
VBUS | - | - | USB2_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
ID | - | - | OTG2_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U17). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address 0x57.
General purpose RAM is accessed at I2C slave address 0x6F.
This RTC IC is supported in Linux so it can be used as hwclock device.
The TE0782 is also equipped with a Silicon Labs I2C-programmable clock generator Si5338A (U2). The Si5338 can be programmed using the I2C-bus, to change the frequency on its outputs. It is accessible on the I2C slave address 0x70.
PLL connection:
Input/Output | Default Frequency | Notes |
---|---|---|
IN1/IN2 | Externally supplied | need decoupling on base board |
IN3 | 25MHz | Fixed input clock |
IN5 | - | not available and not used |
IN4/IN6 | - | connected to Ground |
CLK0 A/B | - | GT REFCLK0 |
CLK1 A/B | - | GT REFCLK3 |
CLK2 A/B | - | GT REFCLK6 |
CLK3 A/B | - | GT REFCLK5 |
Two Microchip 24AA025E48 EEPROMs (U22 and U24) are used on the TE0782. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. Those are accessible by the I2C slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .
For startup, a power supply with minimum current capability of 3A is recommended.
VIN and 3.3VIN can be connected to the same source (3.3 V).
Supply Voltage | Voltage Range | note |
---|---|---|
Vin | 3.3 V to 5.5 V | Typical 200 mA, depending on customer design and connections |
Vin 3.3V | 3.3 V | Typical 50 mA, depending on customer design and connections |
Bank | Voltage | max. Value | note |
---|---|---|---|
0 | 3,3 V | - | FPGA Configuration |
502 | 1,5 V | - | DDR3-RAM Port |
109 / 110 / 111 / 112 | 1,2 V | - | FPGA MGT |
500 / 501 | 3,3 V | - | MIO Banks |
9 | 1,8 V | - | ETH2 RGMII |
10 | user | 3,3 V | B2B name: VCCIO_10 |
11 | user | 3,3 V | B2B name: VCCIO_11 |
12 | user | 3,3 V | B2B name: VCCIO_12 |
13 | user | 3,3 V | B2B name: VCCIO_13 |
33 | user | 3,3 V | B2B name: VCCIO_33 |
34 | user | 3,3 V | B2B name: VCCIO_34 |
35 | 1,8 V | - | Hyper-RAM, Ethernet, I2C |
Storage device name | Content | Notes |
---|---|---|
24LC128-I/ST | not programmed | User content |
24AA025E48 EEPROMs | User content not programmed | Valid MAC Address from manufacturer |
e-MMC Flash-Memory | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
HyperFlash RAM | not programmed | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed |
Revision | Changes |
---|---|
01 | Prototypes |
02 | First production release |
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | V | |
Vin33 supply voltage | -0.4 | 3.6 | V | |
VBat supply voltage | -1 | 6.0 | V | |
PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | |
I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0782 does not have HP banks |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal |
Storage Temperature | -40 | +85 | C | |
Storage Temperature without the ISL12020MIRZ | -55 | +100 | C |
Assembly variants for higher storage temperature range on request |
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex). |
Parameter | Min | Max | Units | Notes | Reference document |
---|---|---|---|---|---|
Vin supply voltage | 2.5 | 5.5 | V | ||
Vin33 supply voltage | 3.135 | 3.465 | V | ||
VBat supply voltage | 2.7 | 5.5 | V | ||
PL IO Bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx document DS191 | |
I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx document DS191 and DS187 |
Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Module size: 76 mm × 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm.
Commercial grade modules
All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weigt | Part |
---|---|
g | Plain module |
g | Set of bolts and nuts |
date | revision | authors | description |
---|---|---|---|
2016-06-27 | v10 | initial release |