Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.



Table of Contents

Overview


The Trenz Electronic TE0703 Carrier Board is a base-board for 4 x 5 SoMs, which exposes the MIO- and the PS/PL-pins of the SoM to accessible connectors and provides a whole range of on-board-components to test and evaluate Trenz Electronic 4 x 5 SoMs.

See page "4 x 5 cm carriers" to get information about the SoM's supported by the TE0703 Carrier Board.

Refer to http://trenz.org/te0703-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups:

  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Samtec Razor Beam™ LSHM-150 B2B connector, JB1
  2. Samtec Razor Beam™ LSHM-150 B2B connector, JB2
  3. Samtec Razor Beam™ LSHM-130 B2B connector, JB3
  4. Micro SD card socket with detect switch, J3
  5. LED indicators D1 and D2
  6. Mini-USB type B connector, J4
  7. LED indicators D3 and D4
  8. Configuration DIP switches, S2 (see table under "DIP switches" section)
  9. User push button (Reset), S1
  10. External connector (VG96) placeholder, J1
  11. External connector (VG96) placeholder, J2
  12. VCCIO voltage selection jumper block, J5, J8, J9 and J10 (see "Power and Power-On Sequence" section)
  13. Trxcom 1000Base-T Gigabit RJ45 Magjack, J14 with 4 integrated LEDs
  14. USB type A receptacle, J6 (optional micro USB 2.0 type A/B receptacle available, J12)
  15. 5V power connector jack, J13
  16. SD IO voltage (VCCA) selection jumper J11

Initial Delivery State

Storage device name

Content

Notes

FTDI chip configuration EEPROM U10Xilinx License

Do not overwrite, see warning in related section

System Controller CPLD U5SC CPLD Firmware-


Board is shipped in following configuration:

SwitchPositionDescription
S2-1ONMode control MC1.
S2-2ONFPGA access on module (need also S2-3 ON)

S2-3

ONFPGA access on module (need also S2-2 ON)
S2-4OFFBoot mode set to QSPI.


Different delivery configurations are available upon request.

Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

The configuration signals are managed by the CPLD and therefore Firmware dependet. Standart configuration is given below.

Control signal

Switch /Button/ LED /Pin

Signal Schematic NamesConnecte toFunctionalityNotes
Module  JTAG selectDip switche S2-2CM0SC CPLD pin 75

ON: Module JTAG access ( if S2-3 ON)

OFF: Module CPLD JTAG access ( if S2-3 ON)

TE0703 CPLD - CC703S#CC703S-JTAG
Module JTAG selectSC CPLD pin 104PROGMODEB2B JB1 pin 90Module JTAG select: Module CPLD high or SoC/FPGA JTAG low ; via CPLD firmware linked to CM0TE0703 CPLD - CC703S#CC703S-JTAG
Carrier CPLD JTAG enable

Dip switch S2-3

JTAGEN

SC CPLD pin 120

ON: SoM JTAG access

OFF: Carrier SC CPLD JTAG access

TE0703 CPLD - CC703S#CC703S-JTAG
Select boot modeDip switche S2-4MIO0

SC CPLD pin 94

and B2B JB1 pin 88

ON: Boot from SD Card

OFF: Boot from QSPI flash on module

TE0703 CPLD - CC703S#CC703S-BootMode
Boot Mode is also module dependent
Select boot modeSC CPLD pin 83

MODE

B2B JB1 pin 31SD-CARD (Zynq) or QSPI-Flash; via CPLD firmware linked to MIO0TE0703 CPLD - CC703S#CC703S-BootMode
Boot Mode is also module dependent
ResetS1S1SC CPLD pin114global resetTE0703 CPLD - CC703S#CC703S-Reset
ResetSC CPLD pin 119RESINB2B JB2 pin 17via CPLD firmware linked to S1TE0703 CPLD - CC703S#CC703S-Reset
Moduel enableSC CPLD pin 81

EN1

B2B JB1 pin 27Module power enablepulled up by CPLD
Disable CPLD power ManagementSC CPLD pin 78NOSEQB2B JB1 pin 8Disable CPLD power managementpulled up by CPLD
Disable Card detect pinDip switche S2-1

CM1

SC CPLD pin 76

ON: Force CD Pin to module to GND

OFF: Set CD Pin to module to SD CD Pin

TE0703 CPLD - CC703S#CC703S-SD
SD Card detectSD Card Socket J3 pin 9SD_CDSC CPLD pin93Low if Card detectedTE0703 CPLD - CC703S#CC703S-SD
SD SelectorSC CPLD pin 113SD_SELU2 pin 24FIXed to GND: Select SD Card  (CPLD SD port not used)TE0703 CPLD - CC703S not used


Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the B2B connector: 

B2B ConnectorInterfacesI/O Signal CountNotes
JB1User IO48 single ended or 24 differentialAvailable on J1
I²C2MIO10, MIO11, available on J1
SD IO6-
primary UART2MIO14, MIO15; CPLD Firmware dependent
secondary UART2MIO12, MIO13; CPLD Firmware dependent
GbE PHY_MDIO8-
Control Signals7including MIO0 and MIO9; CPLD Firmware dependent
VBAT1-
JB2User IO36 single ended or 18 differentialAvailable on J1
USB OTG5Including USB-VBUS and VBUS_V_EN
JB3User IO66 single ended or 33 differentialAvailable on J2
LEDs2-
JTAG4-
Control Signal1Reset


Micro SD Card Socket

Micro SD card socket is connected to the B2B connector through a Texas Instruments TXS02612 SDIO port expander for voltage translation. The Micro SD card has 3.3V signal voltage level while most 4 x 5 modules use 1.8V for the SD card interface.

Connected ToSignal NameNotes
U5-93SD-CDManaged CPLD Firmware
JB1-28SD-DAT0-
JB1-26SD-CMD-
JB1-24SD-CCLK-
JB1-22SD-DAT1-
JB1-20SD-DAT2-
JB1-18SD-DAT3-



USB Interface

TE0703 board has two physical USB sockets:

USB ConnectorSignalConnected to
J4DL_NU4-7
DL_PU4-8
J6 or J12OTG-D_PJB3-48
OTG-D_NJB3-50
(J12 only)OTG-IDJB3-52


Ethernet 

On-board Ethernet jack J14 pins are routed to B2B connector JB1. Ethernet jack J14 LED signals PHY_LED1, PHY_LED2, PHYLED1R and PHYLED2R are all routed to System Controller CPLD bank 1.

Ethernet PHY connection

MagJackSignalB2B
J14A-2PHY_MDI0_PJB1-3
J14A-3PHY_MDI0_NJB1-5
J14A-4PHY_MDI1_PJB1-9
J14A-5PHY_MDI1_NJB1-11
J14A-6PHY_MDI2_PJB1-15
J14A-7PHY_MDI2_NJB1-17
J14A-8PHY_MDI3_PJB1-21
J14A-9PHY_MDI3_NJB1-23
J14BPHY_LED1U5-86
J14BPHY_LED1RU5-92

J14C

PHY_LED2U5-85
J14CPHY_LED2RU5-91


External VG96 Connector I/Os

I/O signals connected to the B2B connector: 

B2B ConnectorInterfacesI/O Signal CountNotes
J1User IO48 single ended or 24 differentialFrom JB1 (group1)
User IO36 single ended or 18 differentialFrom JB3 (group2)
I²C2
J2User IO48 single ended or 24 differentialFrom JB2 (group4)
User IO18 single ended or 9 differentialFrom JB2 (group3)
CPLD User IO18 single endedIncluding UART 2 on X16, X17; CPLD Firmware dependent


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

USB to JTAG and UART bridge

TE0703 has on-board USB JTAG and UART solution based on UART/FIFO controller from FTDI (U4). FTDI EEPROM is pre-programmed with license code to support Xilinx programming tools.

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

JTAG and UART signals along with some more FTDI IOs are routed to the CPLD. See CPLD Firmware TE0703 CPLD - CC703S#CC703S for further description.

Signal

B2B Connector Pin

Note
M_TCKU5-131CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, dependent on Dip switches linked to Module JTAG Port on JB2.
M_TDIU5-136
M_TDOU5-137
M_TMSU5-130
FT_B_TXU5-139CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, linked to Module primary UART on JB1.
FT_B_RXU5-138
ADBUS7U5-142CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, currently not used.
ADBUS4U5-143
ACBUS4U5-141
ACBUS5

U5-140

BDBUS2U5-133
BDBUS3U5-132
BDBUS4U5-128
BDBUS5U5-127
BDBUS6U5-126
BDBUS7U5-125
BCBUS0U5-122
BCBUS1U5-121


CPLD

TE0703-06 has a Lattice LCMXO2-1200HC as a system controller. for further function description see Firmware TE0703 CPLD - CC703S#CC703S,

SD IO Levelshifter

SD IO levelshifter (U2) is used in congntion with jumper J11 to select the correct SD IO interface voltage of the SoM. 

I2C Repeater

For power sequence reasons the I2C bus is routed via a repater (U7) to to ensure no IOs of the SoM are driven before M3.3VOUT is up.

LEDs

There are four on-board LEDs. D3 and D4 are  connected to the B2B connector JB2 pins FLED1 and FLED2 respectively and can be read by CPLD firmware. See TE0703 CPLD - CC703S#CC703S-LED.

LEDColorSignalConnected toDescription
D1RedULED1U5-117FTDI UART receive activity.
D2GreenULED2U5-115FTDI UART transmit activity.
D3RedFLED1JB2-99Module LED, CPLD can read status via signal FL_0 connected via 10K.
D4GreenFLED2JB2-90Module LED, CPLD can read status via signal FL_1 connected via 10K.


DIP switches

DIP switch settings are CPLD Firmware dependent, default firmware:

SwitchONOFFNotes
S2-1Set PGOOD pin to low ('0') / Force CD pin to module to high impedance ('Z')Set PGOOD pin to high ('1') / Set CD pin to module to SD_CD pinTE0703 CPLD - CC703S#CC703S-BootMode /  TE0703 CPLD - CC703S#CC703S-SD
S2-2Module FPGA  JTAG access ( if S2-3 ON)Module CPLD JTAG access ( if S2-3 ON)TE0703 CPLD - CC703S#CC703S-JTAG
S2-3Module FPGA/CPLD  JTAG access (depends on S2-2)Carrier CPLD  JTAG accessTE0703 CPLD - CC703S#CC703S-JTAG
S2-4Boot from SD Card (Set pin to GND)Boot from QSPI flash on module (Set pin to VDD)

TE0703 CPLD - CC703S#CC703S-BootMode
Boot Mode also depends on module.


Mode status is displayed on TE0703 LEDs, see TE0703 CPLD - CC703S#CC703S-LED.

Jumper

TE0703-06 has 5 Voltage selection jumpers. Select 1.8V or 3.3V in accordenc of the attached module capabilities and your needs. Refer to the 4 x 5 Module Integration Guide for VCCIO voltages options.

Power RailJumper

1.8V

3.3VNotes
VCCIOAJ51-22-3-
VCCIOBJ81-22-3-
VCCIOCJ91-22-3-
VCCIODJ101-22-3-
VCCAJ111-22-3SD IO level shifter voltage selection (module side), compare with TRM of attached Module







Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.

Power

Power supply with minimum current capability of 3A for system startup is recommended.

Power Supply

Single power supply with minimum current capability of 3A at 5V for system startup is recommended.

Power Consumption

Power Input PinMax Current
VIN (power connector jack J13)4A


Typical power consumption for TE0703-05 + TE0715-01 module with SD micro card inserted, Ethernet connected and link up, system booted into Linux prompt and idling is 5V / 0.55A.

Power-On Sequence

It is not allowed to feed any voltage to any external I/O pin before there is no power indication on M3.3VOUT pins. Presence of 3.3V on B2B JB2 connector pins 9 and 11 indicates that module is properly powered up and ready.

If any of the VCCIOA, VCCIOB, VCCIOC or VCCIOD will be powered through external connectors J1 or J2, then corresponding VCCIO jumper should also be removed.

Power Rails


Power Rail Name

Connector-Pin

DirectionNotes
5VINJ13-1in5 V power input
VIN- -5 V power input after protection
3.3VJB1-2, 4, 6, 14, 16outGeneratet from VIN by DCDC U3,  constant 3.3V rail
M1.8VOUTJB1-40 in1.8V from Module.
M3.3VOUTJB2-9, 11in3.3V from Module.
VCCIOAJB1-10, 12outUse jumper J5  to source by M1.8VOUT or M3.3VOUT.
VCCIOBJB2-2 ,4outUse jumper J8  to source by M1.8VOUT or M3.3VOUT.
VCCIOCJB2-6outUse jumper J9  to source by M1.8VOUT or M3.3VOUT.

VCCIOD

JB2-8, 10outUse jumper J10  to source by M1.8VOUT or M3.3VOUT.
VCCA--SD IO leveshifter voltge on Module side. Use jumper J11 to source by M1.8VOUT or M3.3VOUT.
VCCJTAGJB2-92inJTAG reference voltage
USB-VBUS_RJ6-1 (J12-1)out5V USB, derived from VIN by power switch U1


Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference document

5VIN supply voltage

 -0.3

7

V

MP5010A, EN6347QI data sheet

Storage temperature

-40

+100

°C

ROHM Semiconductor SML-P11 Series datasheet

Recommended Operating Conditions

Parameter

MinMax

Units

Reference document

5VIN supply voltage

4.75

5.25

V

USB2.0 specification concerning 'VBUS' voltage
Operating temperature

-40

+85

°C

FTDI FT2232H datasheet


Assembly variants for higher storage temperature range are available on request.


Please check components datasheets for complete list of absolute maximum and recommended operating ratings.

Physical Dimensions

 All dimensions are given in millimeters.


In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .







Operating Temperature Ranges

The carrier board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted modules which determines the relevant operating temperature range of the overall system.

Weight

42g - Plain board.

13g - 2 x VG96 connectors.

Revision History

Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TE0728 overview page
English pageGerman page


Hardware Revision History

Date

Revision

Notes

PCN

Documents
2023-09-0407

See Revision changes.



2019-09-0206

Added SD IO voltage selection jumper

Further changes  see PCN.

PCN-20190104TE0703

2016-09-07

05

Added VCCIO Jumpers

PCN-20161122

TE0703-05

-

04

Corrected FTDI EEPROM connection

-

TE0703-04

-

03

Added VCCIO strapping resistors

-


-

02

First series boards

-


-

01

Prototypes

-


Hardware revision number is printed on the PCB board next to the module model number separated by the dash.


Document Change History

Date

Revision

Contributors

Description

  • updated to REV07
2022-09-23v.44Mohsen Chamanbaz
  • Changing in the dip-switches table because of updating of CPLD firmware (CPLD Firmware REV03)
2019-10-07v.43Martin Rohrmüller
  • updated to REV06
  • updated to TRM style 2.12

2018-06-13


v.29

Ali Naseri
  • updating operating conditions
2017-02-07v.28John Hartfiel
  • Add DIP setting description
2017-11-09v.26John Hartfiel
  • add B2B connector section
2017-02-21

v.19


Jan Kumann
  • New block diagram.
2017-02-02

v.16

Jan Kumann
  • New board image with silk screen pin markings for VG96 connectors J1 and J2.
2016-12-22

v.14

Jan Kumann
  • Block diagram added.
2016-12-08
v.10

Jan Kumann

  • Document structure revised.
2016-12-05

v.5

John Hartfiel
  • Corrected Boot Mode table.
2016-09-06

v.1

Jan Kumann, John Hartfiel

  • Initial document.

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