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Table of Contents
Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TEC0330/REV03 for downloadable version of this manual and additional technical documentation of the product.
The Trenz Electronic TEC0330 FPGA board is a PCI Express form factor card (PCIe 2.0 or higher) integrating the Xilinx Virtex-7 XC7VX330T FPGA chip. This high-end FPGA card is designed for maximum system performance and intended for use in applications with high demands on system throughput. There is a SO-DIMM socket on the board for standard DDR3 SDRAM extension memory module.
The TEC0330 features HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard I/O Mezzanine modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD, and also connector with 5 high-speed I/O differential signaling pairs.
The TEC0330 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host systems, it can not be used as a stand-alone device.
Additional assembly options are available for cost or performance optimization upon request.
TEC0330-03 block diagram.
Figure 2: FPGA board TEC0330-03.
|Storage device name|
SPI Flash OTP Area
Empty, not programmed
Except serial number programmed by flash vendor.
SPI Flash Quad Enable bit
SPI Flash main array
Table 1: Initial delivery state.
The high-pin count (HPC) FMC (FPGA Mezzanine Card) connector (J2) is a standard ANSI/VITA 57.1 modular interface to the FPGA and provides access to numerous FPGA I/O pins for use by other mezzanine modules and expansion cards. The FMC connector supports single ended I/O (with several VCCIO voltages available) and LVDS I/O signaling.
The I/O signals are routed from the FPGA I/O banks to the FMC connector as LVDS pairs:
|FPGA Bank||I/O Signals||LVDS pairs||Bank Voltage (VCCO)||Notes|
Bank voltage VIO_B_FMC must be supplied by FMC connector pins J2-J39, J2-K40.
Bank's VREF_B_M2C signal is routed to the FMC connector pin J2-K1 (external reference voltage).
|Bank 37||34||17||1.8V||Bank's VREF_A_M2C signal is routed to the FMC connector pin J2-H1 (external reference voltage).|
|Bank 38||34||17||1.8V||Bank's VREF_A_M2C signal is routed to the FMC connector pin J2-H1 (external reference voltage).|
Table 2: Overview of the FPGA I/O bank signals routed to the FMC.
There are also 10 high-speed MGT lanes (Xilinx GTH transceivers) from different FPGA MGT banks routed to the FMC connector. Following MGT lanes are available on the FMC connector:
|FPGA Bank||I/O Signals||LVDS Pairs||MGT Lanes||MGT Bank's Reference Clock|
|116||8||4||2||1 clock-signal from clock synthesizer U9 to bank's pins T6/T5.|
|117||16||8||4||2 clock-signals from clock FMC connector GBTCLK0_M2C and GBTCLK1_M2C (pins J2-D4/J2-D5 and J2-B20/J2-B21) to bank's pins M6/M5 and P6/P5.|
1 reference clock from clock synthesizer U9 to bank's pins F6/F5
1 reference clock from programmable quad clock generator U13 to bank's pins H6/H5.
Table 3: Overview of MGT banks lanes routed to the FMC connector.
The FMC connector has also two reference clock input pairs (LVDS) routed to the FPGA MGT bank 117, see also section MGT lanes.
There are also JTAG, I2C interface and power good control signals routed between FMC connector and System Controller CPLD:
|Interface||I/O Signals||Schematic Name / FMC Pin||Connected to||Notes|
FMC_TRST, pin D34
FMC_TCK, pin D29
FMC_TMS, pin D33
FMC_TDI, pin D30
FMC_TDO, pin D31
|SC CPLD, bank 2||VCCIO: 3V3PCI.|
FMC_SCL, pin C30
FMC_SDA, pin C31
|SC CPLD, bank 2|
I2C-lines 3V3PCI pulled-up.
FMC_PRSNT_M2C_L, pin H2
FMC_PG_C2M, pin D1 (3V3FMC pull-up)
FMC_PG_M2C, pin F1 (3V3FMC pull-up)
|SC CPLD, bank 1|
PG - Power Good signal.
C2M - carrier to mezzanine module.
M2C - mezzanine module to carrier.
Internal System Controller CPLD signal assignment:
FEX_0_N <= FMC_PG_M2C
FMC_PG_C2M <= FMC_PRSNT_M2C_L
Table 4: FMC connector pin-outs of available interfaces to the System Controller CPLD.
FPGA bank 17 and 18 clock inputs from FMC connector:
|Schematic Name||FMC Connector Pins||FPGA Bank||FPGA Pins|
|CLK0_P, CLK0_N||H4, H5||17||R28, R29|
|CLK1_P, CLK1_N||G2, G3||17||P29, P30|
|CLK2_P, CLK2_N||K4, K5||18||G31, G31|
|CLK3_P, CLK3_N||J2, J3||18||H29, H30|
Table 5: FMC connector pin-outs for reference clock input.
Several VCCIO voltages are available on the FMC connector for FPGA I/O banks:
|Schematic Name||Max Current||FMC Connector Pins||Notes|
|12V||1A||C35, C37||Externally supplied 12V|
|3V3PCI||20mA||D32||Supplied by the PCIe interface|
|3V3FMC||3A||D36, D38, D40, C39||Supplied by DC-DC converter U15|
|VIO_B_FMC||External supply||J39, K40||Externally supplied VCCO to HB FPGA bank 39|
|FMC_VADJ||4A||H40, G39, F40, E39||Fixed to 1.8V, supplied by DC-DC converter U7|
Table 6: Available VCCIO voltages on FMC connector.
The TEC0330 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable. See next section for the overview of FPGA MGT lanes routed to the PCIe interface.
MGT (Multi Gigabit Transceiver) lane consists of one receive and one transmit (RX/TX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin connection and FPGA pin connection information.
FPGA to FMC Connector MGT lanes
|Lane||FPGA Bank||Type||Signal Name||FPGA Pin||FMC Pin|
Table 8: FPGA to FMC connector MGT lanes overview (continue on next page).
FPGA to FMC Connector MGT lanes (continued)
|Lane||FPGA Bank||Type||Signal Name||FPGA Pin||FMC Pin|
Table 8: FPGA to FMC connector MGT lanes overview.
FPGA to PCIe Connector MGT lanes
|Lane||FPGA Bank||Type||Signal Name||FPGA Pin||PCIe Pin|
Table 9: FPGA to PCIe connector MGT lanes overview.
Following table lists reference clock sources of the MGT banks.
|Clock Signal||MGT Bank||Source||FPGA Pin||Notes|
|MGTCLK_5338_P||115||U13, CLK1A||MGTREFCLK0P_115, AB6||On-board Si5338A.|
|MGTCLK_5338_N||115||U13, CLK1B||MGTREFCLK0N_115, AB5||On-board Si5338A.|
|PCIE_CLK_P||115||J1-A13, REFCLK+||MGTREFCLK1P_115, AD6||External clock from PCIe slot.|
|PCIE_CLK_N||115||J1-A14, REFCLK-||MGTREFCLK1N_115, AD6||External clock from PCIe slot.|
|CLK_SYNTH_DCLKOUT4_P||116||U9, DCLKout4||MGTREFCLK0P_116, T6||On-board LMK04828B.|
|CLK_SYNTH_DCLKOUT4_N||116||U9, DCLKout4*||MGTREFCLK0N_116, T6||On-board LMK04828B.|
|GBTCLK0_M2C_P||117||J2-D4||MGTREFCLK0P_117, M6||External clock from FMC connector.|
|J2-D5||MGTREFCLK0N_117, M5||External clock from FMC connector.|
|GBTCLK1_M2C_P||117||J2-B20||MGTREFCLK1P_117, P6||External clock from FMC connector.|
|GBTCLK1_M2C_N||117||J2-B21||MGTREFCLK1N_117, P5||External clock from FMC connector.|
|CLK_SYNTH_SDCLKOUT7_P||118||U9, DCLKout7||MGTREFCLK0P_118,F6||On-board LMK04828B.|
|CLK_SYNTH_SDCLKOUT7_N||118||U9, DCLKout7*||MGTREFCLK0N_118,F5||On-board LMK04828B.|
|MGTCLK2_5338_P||118||U13, CLK3A||MGTREFCLK1P_118, H6||On-board Si5338A.|
|MGTCLK2_5338_N||118||U13, CLK3B||MGTREFCLK1N_118, H5||On-board Si5338A.|
Table 10: MGT banks reference clock sources.
There are three JTAG interfaces available on the TEC0330 board:
|JTAG Interface||Signal Schematic Name||JTAG Connector Pin||Connected to|
|CPLD_JTAG_TMS||J8-1||SC CPLD, bank 0, pin 90|
|CPLD_JTAG_TDI||J8-2||SC CPLD, bank 0, pin 94|
|CPLD_JTAG_TDO||J8-3||SC CPLD, bank 0, pin 95|
|SC CPLD, bank 0, pin 91|
|FPGA_JTAG_TMS||J9-4||FPGA, bank 0, pin N9|
|FPGA_JTAG_TMS||J9-6||FPGA, bank 0, pin M8|
|FPGA_JTAG_TCK||J9-8||FPGA, bank 0, pin N8|
|FPGA_JTAG_TDI||J9-10||FPGA, bank 0, pin L8|
|FMC_TRST||J2-D34||SC CPLD, bank 2, pin 36|
|FMC_TRST||J2-D29||SC CPLD, bank 2, pin 27|
|FMC_TCK||J2-D33||SC CPLD, bank 2, pin 28|
|FMC_TMS||J2-D30||SC CPLD, bank 2, pin 31|
|FMC_TDO||J2-D31||SC CPLD, bank 2, pin 32|
Table 11: JTAG interfaces on TEC0330 board.
The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA module and to display its programming state.
|SC CPLD Bank||CPLD Bank's VCCIO|
Table 12: VCCIO voltages of CPLD banks.
Following table describes the interfaces and functionalities of the System Controller CPLD not described elsewhere in this TRM:
|CPLD Functionality||Interface||Designated CPLD Pins||Connected to||Notes|
|I2C interface between on-board peripherals and FPGA||I2C|
VCCIO: 1V8, all with pull-up to 1V8.
Following devices and connectors are linked to the FPGA_IIC I2C interface:
Note: FPGA_IIC_OE must kept high for I2C operation.
For I2C slave device addresses refer to the component datasheets.
External LVDS pairs
5 x LVDS pairs
Can also be used for single-ended signaling.
Internal LVDS pairs
6 x LVDS pairs
Can also be used for single-ended signaling.
FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK).
Internal signal assignment:
FEX_DIR <= FMC_PRSNT_M2C_L
|FPGA programming control and state||2 I/Os||VCCIO: 1V8|
|I2C interface to programmable quad clock generator||I2C|
Only PLL_SDA has 1V8 pull-up.
|Fan PWM control J4||2 I/Os|
Internal signal assignment:
|Button S2||1 I/O||Functionality depends on CPLD firmware, activating pin PROGRAM_B (active low) and LED1 in standard configuration.|
Fast blinking, when FPGA is not programmed.
Internal signal assignment:
PCIe control line RESET_B
Internal signal assignment:
Control interface to clock synthesizer U9 (TI LMK04828B)
SPI (3 I/Os),
Pull up to 3V3PCI.
|Control Interface to DC-DC converters U3 and U4 (both LTM4676)|
I2C (2 I/Os),
LTM I2C interface is also accessible trough header J10.
LTM1_ALERT and LTM2_ALERT signals are not used.
|Power-on sequence and monitoring||6 I/Os|
Sequence of the supply voltages depend on the System Controller CPLD firmware.
EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.
PG signals will not be evaluated.
Table 13: Overview of the System Controller CPLD functions.
The TEC0330 board supports additional DDR3 SO-DIMM via 204-pin socket U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.
The reference clock signal for the DDR3 interface is generated by the quad programmable clock generator U13 and is applied to the FPGA bank 35.
There is also a I2C interface between the System Controller CPLD and the DDR3 SDRAM memory:
|Interface Signals Schematic Name||System Controller CPLD Pin||DDR3 Memory Interface Pin|
|DDR3_SDA||Bank 2, pin 48||Pin 200 (3V3PCI pull-up)|
|DDR3_SCL||Bank 2, pin 49||Pin 202 (3V3PCI pull-up)|
Table 14: I2C-interface between SC CPLD and DDR3 SDRAM memory.
An 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.
The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.
List of on-board and external reference clock signals of the TE0330 board:
|Clock Source||Schematic Name||Frequency||Clock Destination|
|SMA coaxial connector, J3|
|User||Clock synthesizer U9, pins 37/38|
|RAKON P5146LF oscillator, U11||-||10.0 MHz||Clock synthesizer U9, pins 43/44|
|SiTime SiT8208 oscillator, U14||CLK_25MHz||25.0 MHz||Programmable quad clock generator U13, pin 3|
|FMC connector J2, pins H4/H5|
|User||FPGA bank 17, pins R28/R29|
|FMC connector J2, pins G2/G3||CLK1_P, CLK1_N||User||FPGA bank 17, pins P29/P30|
|FMC connector J2, pins K4/K5||CLK2_P, CLK2_N||User||FPGA bank 18, pins G30/G31|
|FMC connector J2, pins J2/J3||CLK3_P, CLK3_N||User||FPGA bank 18, pins H29/H30|
|FMC connector J2, pins D4/D5|
|User||FPGA bank 117, pins M6/M5|
|FMC connector J2, pins B20/B21|
|User||FPGA bank 117, pins P6/P5|
|PCIe interface J1, pins A13/A14|
|FPGA bank 115, pins AD6/AD5|
Table 15: Clock generator sources overview.
There is a Silicon Labs I2C programmable quad clock generator Si5338A (U13) on-board. It's output frequencies are programmable via FPGA I2C interface using slave device address 0x70 (corresponding I2C logic has to be implemented in FPGA design).
A 25 MHz (U14) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
|Si5338A (U13) Input||Signal Schematic Name||Notes|
Reference clock signal from clock synthesizer U9 (100 nF decoupling capacitors and 100Ω termination resistor).
Reference clock oscillator input, SiTime SiT8208AI (U14).
|25.0 MHz fixed frequency.|
|Connected to the GND.||LSB (pin 'IN4') of the default I²C-adress 0x70 is zero.|
|Si5338A (U13) Output||Signal Schematic Name||Notes|
|DDR3-RAM reference clock signal to FPGA bank 35.|
Reference clock signal to FPGA bank 115 MGT (100 nF decoupling capacitors and 100Ω termination resistor).
Input clock signal to clock synthesizer U9 (100 nF decoupling capacitors).
Reference clock signal to FPGA bank 118 MGT (100 nF decoupling capacitors and 100Ω termination resistor).
Table 16: I/O pin description of programmable clock generator Si5338A.
The TEC0330 board utilizes an ultra low jitter clock synthesizer TI LMK04828B (U9) for conditioning and generating clean clock signals which are necessary for the GTH units of the Xilinx Virtex-7 FPGA module.
The clock synthesizer can be controlled and programmed by its SPI interface (SPI slave) and other control lines, which are routed to the FPGA module (SPI master) and by-passed trough the System Controller CPLD. See section 'System Controller CPLD' for more detailed information.
Logic needs to be generated inside the FPGA module to utilize SPI bus correctly.
|LMK04828B (U9) input||signal schematic name||Note|
|Status_LD1, Status_LD2||LMK_STAT0, LMK_STAT1||Connected to System Controller CPLD, not implemented in current CPLD firmware.|
SPI interface and control lines
|see section 'System controller CPLD'||The clock synthesizer IC is accessible to the FPGA via the SPI interface and control lines, which are routed through the System Controller CPLD.|
Input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitor 100nF.
CLKin0 to connected to GND via serial decoupling capacitor 100nF.
|Input reference clock signal from programmable quad clock generator Si5338A (U13) via serial decoupling capacitor 100nF.|
|OSCin, OSCin*||-||Signal from reference clock oscillator RAKON P51446LF, fixed to 10.0 MHz.|
|LMK04828B (U9) output||signal schematic name||Note|
|Reference clock signal to FPGA bank 15 pins AD29/AE29.|
|Reference clock signal to FPGA bank 15 pins AE31/AF31.|
Reference clock signal to programmable quad clock generator Si5338A (U13) (100 nF decoupling capacitors and 100Ω termination resistor).
|Reference clock signal to FPGA MGT bank 115, pins T6/T5.|
|Reference clock signal to FPGA MGT bank 118, pins F6/F5.|
Reference clock signal to FPGA bank 18, pins J30/J31 (100 nF decoupling capacitors).
Table 17: Pin description of clock synthesizer TI LMK04828B.
6-pin 12V power connector J5 is the main power supply of the TEC0330 FPGA board, minimum current capability of 3A for system startup is recommended.
| Power Input||Typical Current|
Table 18: Typical power consumption.
TBD - To Be Determined.
The on-board voltages of the TEC0330 FPGA board are powered up in predefined sequence after the external voltages 12V on connector J5 and 3V3PCI on connector J1 become available.
Core voltages and main supply voltages have to reach stable state and their "Power Good" signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
Following diagram describes the sequence of enabling the on-board voltages:
Figure 3: FPGA board TEC0330-03 power-on sequence diagram.
|0||1V8||1.8V||HP: 1.2V to 1.8V||Config bank (fixed to 1.8V) / JTAG interface.|
|14||1V8||1.8V||HP: 1.2V to 1.8V||QSPI flash memory interface.|
|15||1V8||1.8V||HP: 1.2V to 1.8V||Reference clock input.|
|16||1V8||1.8V||HP: 1.2V to 1.8V||I2C interface of FPGA.|
|17||1V8||1.8V||HP: 1.2V to 1.8V||Reference clock input.|
|18||1V8||1.8V||HP: 1.2V to 1.8V||Reference clock input / I/O's to CPLD.|
|34||VCC1V5||1.5V||HP: 1.2V to 1.8V||DDR3 memory interface.|
|35||VCC1V5||1.5V||HP: 1.2V to 1.8V||DDR3 memory interface.|
|36||VCC1V5||1.5V||HP: 1.2V to 1.8V||DDR3 memory interface.|
MGT bank supply voltage
MGT bank auxiliary supply voltage
MGT bank termination circuits voltage
|MGT banks with Xilinx GTH transceiver units.|
|19||1V8||1.8V||HP: 1.2V to 1.8V||I/Os routed to FMC, usable as LVDS pairs.|
|37||1V8||1.8V||HP: 1.2V to 1.8V||I/Os routed to FMC, usable as LVDS pairs.|
|38||1V8||1.8V||HP: 1.2V to 1.8V||I/Os routed to FMC, usable as LVDS pairs.|
|39||VIO_B_FMC||user||HP: 1.2V to 1.8V||I/Os routed to FMC, usable as LVDS pairs.|
Table 19: Range of FPGAs bank voltages.
See Xilinx Virtex-7 datasheet (DS183) for the voltage ranges allowed.
|Connector / Pin||Voltage||Direction||Notes|
|J4, pin 2||12V (filtered)||Output||4-wire PWM fan connector supply voltage|
|J6, pin 2||5V (filtered)||Output||Cooling fan M1 supply voltage|
|J8, pin 6||3V3PCI||Output||VCCIO CPLD JTAG|
|J9, pin 2||1V8||Output||VCCIO FPGA JTAG|
|J2, pin C35 / C37||12V||Output||VCCIO FMC|
|J2, pin D32||3V3PCI||Output||VCCIO FMC|
|J2, pin D36 / D38 / D39 / D40||3V3FMC||Output||VCCIO FMC|
|J2, pin H1||VREF_A_M2C||Input||VREF voltage for bank 37 / 38|
|J2, pin K1||VREF_B_M2C||Input||VREF voltage for bank 39|
|J2, pin J39 / J40||VIO_B_FMC||Input||PL I/O voltage bank 39 (VCCO)|
|J2, pin H40 / G39 / F40 / E39||FMC_VADJ||Output||VCCIO FMC (fixed to 1.8V)|
|J1, pin A10 / A11 / B8||3V3PCI||Input||PCIe interface supply voltage|
|J5, pin 1 / 2 / 3||12V||Input||Main power supply connector|
Table 20: Power rails and corresponding connectors of the FPGA board.
12V power supply voltage
|11.4||12.6||V||12V ± 5 %||ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard|
|PL I/O voltage for HP banks||-0.55||VCCO_X + 0.55||V||-||Xilinx datasheet DS183|
|GTH transceivers||-0.5||1.26||V||-||Xilinx datasheet DS183|
|Voltage on System Controller CPLD pins|
MachXO2 family datasheet
|°C||-||MachXO2 family datasheet|
Table 21: Absolute maximum ratings.
|12V power supply voltage||11.4||12.6||V||12V ± 5 %||ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard|
|PL I/O voltage for HP banks||-0.2||VCCO_X + 0.2||V||-||Xilinx datasheet DS183|
|GTH transceivers||(*)||(*)||-||-||Xilinx datasheet DS183|
|Voltage on System Controller CPLD pins||3.135||3.6||V||-||MachXO2 family datasheet|
Table 22: Recommended operation conditions.
|Check Xilinx datasheet (DS183) for complete list of absolute maximum and recommended operating ratings.|
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The FPGA board's operating temperature range depends also on customer design and cooling solution. Please contact us for options.
All dimensions are given in millimeters.
Figure 4: Physical dimensions of the TEC0330-03 board.
|-||03||First production release||-||-|
Table 23: Hardware revision history.
Hardware revision number is printed on the PCB board together with the model number separated by the dash.
Figure 5: TE0330 board hardware revision number.
| Ali Naseri||Initial TRM release.|
Table 24: Document change history.