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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TE0705+CPLD

Table of contents

Overview

CPLD Device with designator U14: LCMX02-1200HC

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
ACBUS4          in96FTDI / currently_not_used
ACBUS5          in88FTDI / currently_not_used
ADBUS4          out98FTDI  / get M_TCK
ADBUS7          out97FTDI / currently_not_used
BDBUS0          inout87FTDI / Module UART0.RX << FTDI
BDBUS1          inout86FTDI  /Module UART0.TX >> FTDI
C_TCKout81JTAG Module
C_TDIout84JTAG Module
C_TDOin83JTAG Module
C_TMSout85JTAG Module
CM0in67DIP Switch S3-M1
CM1in66DIP Switch S3-M2
EN_FMC          out35VADJ Power on
EN1             out53Power Enable Pin for Module CPLD
JTAGEN--82Enable JTAG access to carrier CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
Set DIP Switch S3-JTAGEN to ON, for module access.
JTAGMODEout58Enable JTAG access to module CPLD for Firmware update (zero: JTAG routed to module FPGA, one: Module CPLD access)
M_TCK           in91JTAG FTDI
M_TDI           in94JTAG FTDI
M_TDO           out95JTAG FTDI
M_TMS           in90JTAG FTDI
MIO10           inout32 MIO / used by RGPIO Bus
MIO11           inout31MIO / used by RGPIO Bus
MIO12           inout39 MIO / used by RGPIO Bus
MIO13           inout34 MIO / used by RGPIO Bus
MIO14           inout40MIO / Module UART0.RX << BDBUS0
MIO15           inout30MIO / Module  UART0.TX >> BDBUS1
MODE            out28Boot Mode for Zynq Devices (Flash or SD)
NOSEQ           inout29/ currently_not_used
PGOOD           inout27/ currently_not_used
PHY_LED1        out45LED Ethernet
PHY_LED1_A      out49LED Ethernet / currently_not_used
PHY_LED2        out47LED Ethernet
PHY_LED2_A      out48LED  Ethernet / currently_not_used
POK_FMC         in36FMC VADJ Power Good 
RESIN           out54Module Reset
S1              in75User Button / used by RGPIO Bus
S2              in74User Button / Global Reset
SD_DETECT       in42SD Detection / used for FPGA Boot Mode
SD_WP           in43SD / RGPIO Bus
ULED1           out78LED D6
ULED2           out77LED D7
ULED3           out76LED D8
ULED4           out65LED D9
ULED5           out71LED D4
ULED6           out70LED D15
ULED7           out69LED D14
ULED8           out68LED D5
USB_OC          in99USB Over Current
USR0in64DIP Switch S4-1 / used by RGPIO Bus (PCB REV04 only)
USR1in61DIP Switch S4-2 / used by RGPIO Bus (PCB REV04 only)
USR2in60DIP Switch S4-3 / used by RGPIO Bus (PCB REV04 only)
USR3in59DIP Switch S4-4 / used by RGPIO Bus (PCB REV04 only)
VID0            out37VADJ Voltage selection (EN5335QI)
VID1            out38VADJ Voltage selection (EN5335QI)
VID2            out41VADJ Voltage selection (EN5335QI)
X6              in19RGPIO Bus
Y0               15/ currently_not_used
Y1               14/ currently_not_used
Y2              in13RGPIO CLK
Y3              out10RGPIO TX
Y4              in9RGPIO RX
Y5               8/ currently_not_used
Y6              in7RGPIO Bus

 

Functional Description

JTAG

JTAGEN set carrier board CPLD into the chain for firmware update. In normal mode JTAG is routed directly to Module. Set S3-ENJTAG to OFF to get access to carrier CPLD.

JTAGMODE set module CPLD into the chain for firmware update. In normal mode  JTAG is routed directly to FPGA. Set S3-ENJTAG, S3-M1 and S3-M2 to ON to get access to module CPLD. Attention VADJ is set to 1.8V in this mode.

Power

EN1 is set to logical one after delay.

EN_FMC is set to logical one after delay.

VADJ Selection Table:

M1M2Description
OFFOFFVADJ: 1.8V
OFFONVADJ: 2.5V
ONOFFVADJ: 3.3V
ONONVADJ: 1.8V, Attention: Also Module CPLD JTAG access is enabled, see JTAG description.

Reset

RESIN (negative Reset) to module, can be set by S2 button.

Boot mode

Boot mode is set to SD-Boot, when SD-Card is detected.

RGPIO

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.

RGPIO Pin to FPGAValue
0MIO10
1MIO11
2MIO12
3MIO13
4MIO14
5MIO15
6-9USR0-USR3 (S4-1...S4-4)
10-11CM0-CM1(S3-M1...S3-M2)
12SD_WP
13SD_DETECT
14USB_OC
15POK_FMC
16S1
17PGOOD
18NOSEQ
19VID0
20X6
21Y6
22VID1
23VID2
24-27reserved
28-31Interface detection
RGPIO Pin from FPGAValue
0-7LED 1-8
08-23unused
24-27reserved
28-31Interface detection

LED

LEDDescription
ULED1not external reset / RGPIO(0), when FPGA Interface is detected
ULED2(M1=off,M2=off) / RGPIO(1), when FPGA Interface is detected
ULED3Module UART0.RX / RGPIO(2), when FPGA Interface is detected
ULED4Module UART0.TX / RGPIO(3), when FPGA Interface is detected
ULED5SD_DETECT / RGPIO(4), when FPGA Interface is detected
ULED6(M1=on,M2=off) / RGPIO(5), when FPGA Interface is detected
ULED7X6 / RGPIO(6), when FPGA Interface is detected
ULED8Y6 / RGPIO(7), when FPGA Interface is detected

 

UART

ToFromDescription
MIO14BDBUS0Module UART0.RX
BDBUS1MIO15Module UART0.TX

 

Appx. A: Change History

Revision Changes

REV01 to REV02

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV02REV03, REV04

document style update
2016-11-17

v.27

 

REV02REV03, REV04John HartfielRevision 02 finished
2016-11-04

 

v.1

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Initial release
 All  

 

Appx. B: Legal Notices