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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TEB0911+Slave+CPLD

Table of contents

Overview

Firmware for PCB-Slave CPLD with designator U83: LCMXO2-1200HC

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
B66_T1           in83FPGA / dp_aux_data_out
B66_T2           in82FPGA / dp_aux_data_oe_n
B66_T3           out81FPGA / dp_aux_data_in
B67_T1           out78FPGA / dp_hot_plug_detect
B67_T2           in76FPGA / currently_not_used
B67_T3           in77FPGA /  / currently_not_used
C_TCK            in131/ currently_not_used
C_TDO            out137/ currently_not_used
C_TDO1/TDI          in136/ currently_not_used
C_TMS            in130/ currently_not_used
CAN_FAULT         26/ currently_not_used
CAN_RX            24/ currently_not_used
CAN_S             25/ currently_not_used
CAN_TX            23/ currently_not_used
DP_AUX_DE        out133Display Port
DP_AUX_RX        in132Display Port
DP_AUX_TX        out138Display Port
DP_TX_HPD        in139Display Port
ERR_OUT          in98FPGA PS / currently_not_used
ERR_STATUS       in97FPGA PS / currently_not_used
ETH_RST          out93Reset
F1_EN            out65FAN
F1PWM            out68FAN
F1SENSE          in67FAN
F2_EN            out61FAN
F2PWM            out110FAN
F2SENSE          in109FAN
F3_EN            out62FAN
F3PWM            out28FAN
F3SENSE          in27FAN
I2C_RST          out94Reset_n for I2C Switches
JTAGENB          --120enable JTAG access to CPLD (one CPLD )
LED_1A           out119Yellow LED
LED_2A           out122Green/Orange LEDs
LED_2B           out121Green/Orange LEDs
LED1             out22Green LED D13
LED2             out21Green LED D14
LED3             out20Green LED D15
LED4             out19Green LED D16
MEM_SCL          in35I2C 100kHz supported
MEM_SDA          inout34I2C
MIO24             95Zynq MIO / currently_not_used
MIO25             96Zynq MIO / currently_not_used
MIO26             42Zynq MIO / currently_not_used
MIO27             57Zynq MIO / currently_not_used
MIO28             44Zynq MIO / currently_not_used
MIO29             59Zynq MIO / currently_not_used
MIO30            in48Zynq MIO / PCIe reset_n
MIO31             54Zynq MIO / currently_not_used
MIO32             60Zynq MIO / currently_not_used
MIO33             41Zynq MIO / currently_not_used
MIO34             58Zynq MIO / currently_not_used
MIO35             43Zynq MIO / currently_not_used
MIO36             50Zynq MIO / currently_not_used
MIO37             55Zynq MIO / currently_not_used
MIO40             56Zynq MIO / currently_not_used
MIO41             52Zynq MIO / currently_not_used
MIO42            out47Zynq MIO / Zynq UART RX
MIO43            in49Zynq MIO / Zynq UART TX
MIO44             45Zynq MIO / currently_not_used
PHY_CLK125M      in85Ethernet
PHY_LED0         in92Ethernet
PHY_LED1         in91Ethernet
PHY_LED2         in86Ethernet
PLL_RST          out73Reset
PLL_SEL0         out74PLL
PLL_SEL1         out75PLL
SC_IO0           in107Master CPLD / Reset
SC_IO1            106Master CPLD / currently_not_used
SC_IO2            105Master CPLD / currently_not_used
SC_IO3           out104Master CPLD / Slave RGPIO TX data 
SC_IO4           in100Master CPLD / Slave RGPIO RX DATA
SC_IO5           in99Master CPLD / Slave RGPIO RX CLK 
SC1_IO_SB         112Master CPLD / currently_not_used
SC2_IO_SB         111Master CPLD / currently_not_used
SD_EN            out38SD Power enable
SD_WP             39SD Write Protection / currently_not_used
SFP_LED1         out142SFP Red LED D2
SFP_LED2         out143SFP Green LED D4
SFP_LED3         out141SFP Red LED D3
SFP_LED4         out140SFP Green LED D5
SFP0_LOS          113SFP / currently_not_used
SFP0_TX_DIS      out115SFP
SFP1_LOS          114SFP / currently_not_used
SFP1_TX_DIS      out117SFP
SFP2_LOS          6SFP / currently_not_used
SFP2_TX_DIS      out10SFP
SSD1_LED         in128SSD
SSD1_PERSTN      out126SSD / Reset_n M2 PCIe
SSD1_SLEEP       in127SSD
SSD1_WAKE        out125SSD
U_SW1            in14Switch S4 / currently_not_used
U_SW2            in13Switch S4 / currently_not_used
U_SW3            in12Switch S4 / currently_not_used
U_SW4            in11Switch S4 / currently_not_used
USB0_RST         out84USB / Reset
USBH_MODE0       out69USB
USBH_MODE1       out71USB
USBH_RST         out70USB / Reset
USR_BUT1         in9Button
XMOD1_A          out1XMOD UART RX
XMOD1_B          in3XMOD UART TX
XMOD1_E          out2XMOD LED
XMOD1_G          in4XMOD Button / Debug Reset

 

Functional Description

JTAG

Used only for CPLD Firmwareupdate. Second chip in JTAG chain when switch S3:2 is ON.

RESET

NameDescription
SSD1_PERSTnSC_IO0
ETH_RSTSlow Reset from SC_IO0
USB0_RSTSlow Reset from SC_IO0
USBH_RSTSlow Reset from SC_IO0
PLL_RSTSlow Reset from SC_IO0

 

LEDs

LEDValueDescription
XMOD1_ECounter Bit or  XMOD1_G 
LED1_1Anot PHY_LED1Yellow LED is PHY RX Indicator (with default PHY settings)
LED_2Anot PHY_LED0Green LED is PHY LINK Indicator (with default PHY settings)
LED_2B0Stub to use only green from dual Green/Orange LED
LED1DP_TX_HPDDisplayPort Hotplug Detection
LED2hub_rst_nUSB hub reset indicator
LED3SSD1_LEDLED output from M2 slot
LED4F1_SENSE 
SFP_LED10 
SFP_LED20 
SFP_LED30 
SFP_LED40 

UART

OutputInput
MIO42XMOD1_B
XMOD1_AMIO43

 

Display Port

OutputInput
DP_AUX_TXB66_T1
DP_AUX_DEnot B66_T2
B66_T3DP_AUX_RX
B67_T1DP_TX_HPD

SD

SD_EN is "0". Enable power for SD slot.

SFP

Transmit for all SFP is enabled.

USB

USB Mode pins constant "11" (default boot mode).

SSD

SSD1_WAKE is "0".

I2C RAM

I2C Baseaddress: 0x74. I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 100 MHz supported.

Write access

Register AddressNameDescription
0FAN CTRL

Enable FAN, Bit 0-2 Fan1 to Fan2, Default all 1

1FAN1 PWMFAN1 PWM (0%-100%, Default 30%)
2FAN2 PWMFAN2 PWM (0%-100%, Default 30%)
3FAN3 PWMFAN3 PWM (0%-100%, Default 30%)

Read access

Register AddressNameDescription
0FAN CTRLFAN Control register
1FAN1 RPSFAN1 Revolutions per second
2FAN2 RPSFAN2 Revolutions per second
3FAN3 RPSFAN3 Revolutions per second

 

FANs

See I2C RAM.

PLL

PLL Selection pins constant "00".

 

RGPIO

RGPIO is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.

RGPIO Pin to FPGAValue
0-2FAN Enable 1..3
3unused
4Slow Reset
5Slow HUB Reset
6unused
7Counter Bit 32
8-23unused
24-27reserved
28-31interface detection
RGPIO Pin from FPGAValue
0-23unused
24-27reserved
28-31interface detection

 

 

Appx. A: Change History

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV01REV01

document style update
2016-11-16v.15REV01REV01

Oleksandr Kiyenko

Revision 01 finished
2016-11-16

v.1

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Initial release
 All  

 

Appx. B: Legal Notices