Table of Contents
Table of Contents |
On https://wiki.trenz-electronic.de/display/PD/TE0714 the online version of this manual and other documents can be found. |
The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
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Top view | Bottom view |
Main Components:
Artix-7 FPGA
B2B-Connectors
Xilinx Artix-7 (A15T, A35T, A50T)
Assembly options for cost or performance optimization available upon request. Possible options:
| Variant | FPGA | GT Clock [MHz] | PL Clock [MHz] | PUDC | GT PWR Enable | B14/Config Voltage [V] | R27 (VCCIO_0 on JM2 Pin 54) | SPI Flash | LED |
|---|---|---|---|---|---|---|---|---|---|
| TE0714-02-35-2I | A35T-2I | 125 | 25 | High | Enabled | 3.3 | JM2 Pin 54 = VCCIO_0 (3.3 V) | S25FL127S | Red |
| TE0714-02-35-2IC6 | A35T-2I | 125 | 25 | High | Enabled | 1.8 | JM2 Pin 54 = Open | N25Q128 | Red |
| TE0714-02-35-2IC7 | A35T-2I | 125 | 25 | Low | Enabled | 3.3 | JM2 Pin 54 = Open | S25FL127S | Red |
| TE0714-02-50-2I | A50T-2I | 125 | 25 | High | Enabled | 3.3 | JM2 Pin 54 = VCCIO_0 (3.3 V) | S25FL127S | Red |
| TE0714-02-50-2IC6 | A50T-2I | 125 | 25 | High | Enabled | 1.8 | JM2 Pin 54 = Open | N25Q128 | Red |
On REV 01 JM2 Pin 54 was GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Boot mode is controlled by the MODE signal on the board to board (B2B) connector:
MODE signal | Boot Mode |
|---|---|
high or open | Master SPI, x4 Mode |
low or ground | Slave SelectMAP |
SPI D2 and D3 have no pull-ups on the module so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
JTAG access to the Xilinx Artix-7 device is provided through connector JM1.
Signal | B2B Pin |
|---|---|
| TCK | JM1: 89 |
| TDI | JM1: 85 |
| TDO | JM1: 87 |
| TMS | JM1: 91 |
Clock | Default Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| CLK125MHz | 25 MHz | U8 | T14 | Frequency depends on Assembly variant |
| MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on Assembly variant |
There is 1 LED on TE0714:
LED | Color | FPGA | Notes |
|---|---|---|---|
D4 | Red | K18 |
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For startup, a power supply with minimum current capability of 1A is recommended.
TE0714 needs one single power supply with nominal 3.3V.
| Test Condition (25C ambient) | Vin Current mA | Notes |
|---|---|---|
| TE0714-35, TEBT0714, empty design, GT not enabled | 110mA |
Power consumption measurements. Actual power consumption depends on the FPGA design and ambient temperature.
Bank | Voltage | Notes |
|---|---|---|
0 Config and B14 | 1.8V or 3.3V | Depends on assembly option |
15 | User | Supplied from base, max 3.3V |
34 | User | Supplied from base, max 3.3V |
Storage device name | Content | Notes |
|---|---|---|
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed |
| PCB Revision | Changes | PCN link | Documentation link |
|---|---|---|---|
01 | Current Hardware Revision, no changes | - | TE0714-01 TRM |
| 02 | VCCIO0 added to B2B | PCN-20160815 |
Parameter | Min | Max | Units | Notes | Reference document |
|---|---|---|---|---|---|
Vin supply voltage | -0.1 | 3.6 | V | ||
| I/O Bank supply voltage | -0.5 | 3.6 | V | Xilinx document DS181 | |
| I/O input voltage for FPGA I/O banks | -0.4 | VCCO_X+0.55 | V | Xilinx document DS181 | |
| GT Transceiver | -0.5 | 1.26 | V | Xilinx document DS181 | |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 1.8V or 3.3V nominal | Xilinx document DS181 |
Storage Temperature | -40 | +85 | C |
| Parameter | Min | Max | Units | Notes | Reference document |
|---|---|---|---|---|---|
| Vin supply voltage | 3.135 | 3.45 | V | ||
| IO Bank supply voltage for I/O banks | 1.14 | 3.465 | V | Xilinx document DS181 | |
| I/O input voltage for I/O banks | -0.20 | Vcco + 0.20 | V | Xilinx document DS181 | |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | For assembly variant with 3.3V CONFIG Bank Option | Xilinx document DS181 |
| Please check Xilinx datasheet for complete list of absolute maximum and recommended operating ratings for the Artix-7 device (DS181). |
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm and can be found here.
Commercial grade modules
All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
| Variant | Weight g | Note |
|---|---|---|
| 2IC6 | 8.3 | Plain Module |
Date | Revision | Authors | Description |
|---|---|---|---|
| 2016-11-18 | Antti Lukats, Thorsten Trenz | changes for REV 02 | |
2016-06-01 | V.9 | initial version |
