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Overview

On https://wiki.trenz-electronic.de/display/PD/TE0714 the online version of this manual and other documents can be found.

The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 Mbyte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.

Block Diagram

Public Docs > TE0714 TRM > TE0714-02 Block diagram by Jan_2.png

Main Components


Top view	Bottom view

Xilinx Artix-7 FPGA, U4
SPI Flash, U7
B2B Connector, JM2
B2B Connector, JM1
MEMS Oscillator (PL Clock), U8
Single Output Low-Dropout Linear Regulator, U6 (1.2V_MGT)
Single Output Low-Dropout Linear Regulator, U5 (1.0V_MGT)
Low-Jitter Precision LVDS Oscillator (GT Clock), U2
Red Indication LED,D4
Step-Down DC-DC Converter, U1 (1.0V)
PFET Load Switch With Configurable Slew Rate, Q1 (3.3V)
Low Power Step-Down DC-DC Converter, U3 (1.8V)
Voltage Detector for Circuit Initialization and Timing Supervision, U23

Key Features

Xilinx Artix-7 (A15T, A35T, A50T)
Rugged for Sock and High Vibration
16 MByte QSPI Flash Memory
Differential MEMS Oscillator for GT Clocking
MEMS Oscillator for PL Clocks (Optional)
Plug-On Module With 2 × 100-Pin High-Speed Hermaphroditic Strips
- 144 FPGA I/O's (Max 68 Differential)
- XADC Analog Input
- 4 GTP (High-Performance Transceiver) Lanes
- GT Reference Clock Input
- Optimized I/O and Power Pins for Good Signal Integrity
On-board High-Efficiency DC-DC Converters
Power Supply for All On-Board Components
eFUSE Bit-Stream Encryption (AES)
One User Configurable LED

Different configurations for cost and performance optimization available upon request. Available options are:

FPGA Type (A15T, A35T, A50T), temperature grade
GT Clock Frequency (or none if not implemented)
PL Clock Frequency and precision (or none if not implemented)
Config and B14 Bank Voltage: 1.8V or 3.3V
SPI Flash type (or none if not implemented)
LED Color (or none if not implemented)
PUDC Pin strapping (pull high or pull down)
GT Power Enable pin strapping (default power enabled or disabled)

Initial Delivery State

Storage device name	Content	Notes
SPI Flash OTP Area	Empty, not programmed	Except serial number programmed by flash vendor
SPI Flash Quad Enable bit	Programmed
SPI Flash main array	demo design
EFUSE USER	Not programmed
EFUSE Security	Not programmed

Signals, Interfaces and Pins

JTAG Interface

JTAG access to the Xilinx Artix-7 device is provided through connector JM1.

Signal Name	B2B Pin
TCK	JM1: 89
TDI	JM1: 85
TDO	JM1: 87
TMS	JM1: 91

Clocking

Clock	Default Frequency	IC	FPGA	Notes
CLK125MHz	25 MHz	U8	T14	Frequency depends on the module variant
MGT_CLK	125MHz	U2	B6/B5	Frequency depends on the module variant

Boot Modes

Boot mode is controlled by the MODE signal on the board to board (B2B) connector:

MODE signal State	Boot Mode
high or open	Master SPI, x4 Mode
low or ground	Slave SelectMAP

SPI D2 and D3 have no pull-ups on the module so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.

LED's

There is one LED on TE0714 module:

LED	Color	FPGA	Notes
D4	Red	K18

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Suppy

TE0714 needs one single power supply with nominal of 3.3V.

Power Consumption

Test Condition (25 °C ambient)	VIN Current mA	Notes
TE0714-35, TEBT0714, empty design, GT not enabled	110mA

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.

Bank Voltages

Bank	Voltage	Notes
0 Config and B14	1.8V or 3.3V	Depends on module variant
15	User	Supplied from baseboard via B2B connector, max 3.3V
34	User	Supplied from baseboard via B2B connector, max 3.3V

Variants Currently In Production

Module Variant	FPGA Chip Model	GT/PL Clock [MHz]	PUDC	GT PWR Enable	B14/Config Voltage [V]	R27 (VCCIO_0 on JM2 Pin 54)	SPI Flash	LED D4
TE0714-02-35-2I	A35T-2I	125/25	High	Enabled	3.3	JM2 Pin 54 = VCCIO_0 (3.3 V)	S25FL127S	Red
TE0714-02-35-2IC6	A35T-2I	125/25	High	Enabled	1.8	JM2 Pin 54 = Open	N25Q128	Red
TE0714-02-35-2IC7	A35T-2I	125/25	Low	Enabled	3.3	JM2 Pin 54 = Open	S25FL127S	Red
TE0714-02-50-2I	A50T-2I	125/25	High	Enabled	3.3	JM2 Pin 54 = VCCIO_0 (3.3 V)	S25FL127S	Red
TE0714-02-50-2IC6	A50T-2I	125/25	High	Enabled	1.8	JM2 Pin 54 = Open	N25Q128	Red

On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module.

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Notes	Reference document
Vin supply voltage	-0.1	3.6	V
I/O Bank supply voltage	-0.5	3.6	V		Xilinx document DS181
I/O input voltage for FPGA I/O banks	-0.4	VCCO_X+0.55	V		Xilinx document DS181
GT Transceiver	-0.5	1.26	V		Xilinx document DS181
Voltage on module JTAG pins	-0.4	VCCO_0+0.55	V	VCCO_0 is 1.8V or 3.3V nominal	Xilinx document DS181
Storage temperature	-40	+85	°C

Recommended Operating Conditions

Parameter	Min	Max	Units	Notes	Reference document
Vin supply voltage	3.135	3.45	V
IO Bank supply voltage for I/O banks	1.14	3.465	V		Xilinx document DS181
I/O input voltage for I/O banks	-0.20	VCCO + 0.20	V		Xilinx document DS181
Voltage on module JTAG pins	3.135	3.465	V	For a module variant with 3.3V CONFIG Bank option	Xilinx document DS181

Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7.

Physical Dimensions

Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.


Top View, Mounting Holes	Bottom View, Samtec Connectors

Operating Temperature Ranges

Commercial grade modules

All parts are at least commercial temperature range of 0 °C to +70 °C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Industrial grade modules

All parts are at least industrial temperature range of -40 °C to +85 °C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Weight

Variant	Weight in g	Note
2IC6	8.3	Plain Module

Revision History

Hardware Revision History

PCB Revision	Changes	PCN link	Documentation link
01	Current Hardware Revision, no changes	-	TE0714-01 TRM
02	VCCIO0 added to B2B	PCN-20160815	-

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Public Docs > TE0714 TRM > TE0714.Rev-Number.jpg

Document Change History

Date	Revision	Authors	Description
2016-12-01		Jan Kumann	Changes in the documant structure, few corrections.
2016-11-18	V.14	Antti Lukats, Thorsten Trenz	Changes for REV 02
2016-06-01	V.9		Initial version