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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware



Table of contents

Overview

Firmware for PCB-Slave CPLD with designator U39. Second CPLD Device in Chain: LCMX02-1200HC

Feature Summary

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
1.8V_EN  / EN_1V8out106Power
5V_EN  / EN_5V       out115Enable 5V, can be permanently enabled by S4-4
C_TCK          131JTAG J28 (XMOD2) / internal currently_not_used
C_TDO          137JTAG J28 (XMOD2) / internal currently_not_used
C_TDO1         136JTAG J28 (XMOD2) / internal currently_not_used
C_TMS          130JTAG J28 (XMOD2) / internal currently_not_used
CLK_A / AUD_CLK        out1AUDIO U3 CLK
CLK_CPLD / MEMS_CLKINin128U25 24,576MHz
DONE          in67PS Done
EN_DDR        out86Enable DDR Power
EN_FMC / FMC_EN    out104FMC
EN_FPD        out81Enable PS FPD Power
EN_GT_L       out77Enable  GT Power
EN_GT_R       out93 Enable GT Power
EN_LPD        out84Enable PS LPL Power
EN_PL         out95Enable PL Power
EN_PLL_PWR    out78Enable SI5345 Power
EN_PSGT / EN_PSGTR      out75Enable  PS GT Power
ERR_OUT  / ERROR    in70PS Error Out / Status / readable via RGIO 
ERR_STATUS  / ERROR_STATin69PS Error Status / Status / readable via RGIO
F1PWM         out121FAN1
F1SENSE       in125FAN1
FAN_FMC_EN  / FMC_FAN_ENout132FMC FAN
FMC_PG_C2M    out141FMC PG
HD_LED_N / HDLED_Nout112J10 HD LED
HD_LED_P / HDLED_Pout110J10 HD LED
HDIO_SC0 / SC0in32FPGA IO /  forward to HD_LED_P / HDLED_P
HDIO_SC1 / SC1in33FPGA IO / currently_not_used 
HDIO_SC2 / SC2in34FPGA IO / currently_not_used
HDIO_SC3 / SC3out35FPGA IO / currently_not_used
HDIO_SC4 / SC4out25FPGA IO / currently_not_used
HDIO_SC5 / SC5out26FPGA IO / RGPIO
HDIO_SC6 / SC6in27FPGA IO / RGPIO CLK
HDIO_SC7 / SC7     in28FPGA IO / RGPIO
I2C_SCL / SCLin50I2C / currently_not_used
I2C_SDA / SCAin52I2C / currently_not_used
INIT_B / INITin68PS init B 
JTAGENB 
120external Pin for CPLD Firmware Update 
LP_GOOD  / PG_LPD    in83LP Power Good
MIO24          38MIO / currently_not_used
MIO25          39MIO / currently_not_used
MIO30         in48MIO / force reboot after FSBL-PLL config for PCIe 
MIO31         in49MIO / PCIe reset 
MIO32           40MIO / currently_not_used
MIO33           41MIO / currently_not_used
MIO34           42MIO / currently_not_used
MIO35           43MIO / currently_not_used
MIO36           44MIO / currently_not_used
MIO37           45MIO / currently_not_used
MIO40in54MIO  / forwarded to PWRLED_P / LED_P 
MIO41          55MIO / currently_not_used
MIO42         out60FPGA UART RX
MIO43         in61FPGA UART TX
MIO44out47MIO /  SD_WP to FPGA  
MOD_EN        out119Module Power 3.3V Enable
MODE0         out6Boot Mode
MODE1         out9Boot Mode
MODE2         out10Boot Mode
MODE3         out11Boot Mode
MR / MRESETnout92PS Reset
PCI_SFP_EN    out76SFP
PER_EN        out117Baseboard Power 3.3V Enable
PERST / PERSTn        out139PCIE Resetn
PG_DDR        in91Power Good / Status / readable via RGIO
PG_FPD        in85Power Good / Status / readable via RGIO
PG_GT_L       in96Power Good / Status / readable via RGIO
PG_GT_R       in94Power Good / Status / readable via RGIO
PG_PL         in82Power Good / Status / readable via RGIO
PG_PLL_1V8 / PG_PLLin73Power Good / Status / readable via RGIO
PG_PSGT       in74Power Good / Status / readable via RGIO
PLL_LOLN / PLL_LOL     in58Module U5 Si5345 / readable via RGIO / currently_not_used
PLL_RST / PLL_RSTn      out56Module U5 Si5345
PLL_SEL0      out57Module U5 Si5345
PLL_SEL1      out59Module U5 Si5345
POK_1V8       in107Power
POK_FMC       in99FMC Power/ readable via RGIO
PROG_B        inout71PS_PROG_B
PSON          out105ATX J20 PS_ON_N
PWR_BTN       in113Power Button S1 or J10
PWRLED_N / LED_Nout111J10 PWR
PWRLED_P / LED_Pout109J10 PWR
PWROK         in100ATX J20 PWROK  / readable via RGIO
RST_BTN       in114Reset Button S2 or J10
S_1 127Beeper/ currently_not_used
SC_IO0 / X0out12Master-Slave SC-Communication / Power Reset
SC_IO1 / X1out13Master-Slave SC-Communication / Power Reset
SC_IO2 / X2out14Master-Slave SC-Communication / currently_not_used
SC_IO3 / X3out20Master-Slave SC-Communication / currently_not_used
SC_IO4 / X4in21Master-Slave SC-Communication /MMC SD WP 
SC_IO5 / X5in22Master-Slave SC-Communication / currently_not_used
SC_IO6 / X6in23Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable)
SC_IO7 / X7       in24Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable)
SC_IO8 / dummy       126/ currently_not_used / ! not available on PCB REV2 !
SC2_SW1       in133S5-1 / Boot Mode Selection / readable via RGIO
SC2_SW2       in138S5-2 / Boot Mode Selection / readable via RGIO
SD_A_EN       out140Micro SD
SD_B_EN       out122MMC SD
SD_CD / SD_CD_OUTout65SD Card detect to FPGA
SD_CD_B       in143MMC SD / readable via RGIO
SD_CD_S       in142Micro SD / readable via RGIO
SEL_SD / SD_SELout62Select SD
SRST_B / SRSTn      out19PS_SRST_B
STAT_LED2 / LED2out98LED D6 Green
STAT_LED3 / LED3out97LED D7 Red
XMOD2_A / XMOD_TXD     out5J12 (XMOD 1)
XMOD2_B / XMOD_RXDin4J12 (XMOD 1)
XMOD2_E  / XMOD_LED   out3J12 (XMOD 1)
XMOD2_G  / XMOD_BTNin2J12 (XMOD 1) / readable via RGIO

 

Functional Description

JTAG

JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.

Power

PSON signal will be enabled/disabled after delay, when Power Button is pressed. Power Button is debounced.

StagePower Enable SignalEnable Power domainNote
1PSON ATX PSON (12V from ATX power supply)Signal will be enabled/disabled after delay, when Power Button is pressed.Power Button is debounced.
2PWROK(ATX Power)

5V_EN (5V)

Note 1: If S4-4 is on, 5V is always on.  S4-4 must be on, if TEBF0808 is used with external 12V instead of ATX Power.
Note 2: CPLD Pullup is used for PWROK to works without external 12V only.

2PWROKMOD_EN (Module 3.3V), EN_LPD, EN_FPD, EN_PLModule B2B connector Main Power and enables
3PG_FPDEN_DDR, EN_PLL_PWR, EN_PSGTRModule periphery power
3PG_PLEN_GT_R, EN_GT_LModule periphery power
4PG_FPD and PG_PLPER_EN(Periphery 3.3V), EN_1V8(Periphery 1.8V), PCI_SFP_EN (PCIe and SFP)Carrier periphery power
4PWROK and PG_FPD and PG_PL and PSON and Master CPLD statusFMC_EN (FMC VADJ)FMC VADJ
5PWROK and PG_FPD and PG_PL and PSON and POK_FMC(VADJ)FMC_PG_C2MFMC supply power status to FMC connector

Note: Power Status is visible on LEDs, see LED section

TE0808 module is not completely powered off with power button, if 12V power jack (J25) is used for power supply. 12V Power ON/OFF is only with ATX power supply usable.

Enable

SD's will be enabled by PWROK and PG_FPD and PG_PL and PSON;.

FMC_FAN_EN will be enabled by PWROK and PG_FPD and PG_PL and PSON_i or RGPIO (11) controlled, when active. F1PWM is constant on.

Reset

Power Button is debounced.

Reset will be also set via modified FSBL, if PCIe is detected.

NameDescription
PLL_RSTnnot RGPIO (0) when active else '1'
SRSTn '1'
MRESETnRST_BTN and PWROK and PG_FPD and PG_PL and PSON and "PS reboot via FSBL"
PERSTnnot RGPIO (1) and MIO31 when active else  rst_btn_i and MIO31
Master CPLD ResetPWROK and PG_FPD and PG_PL and PSON and Reset Button over CPLD interconnect.
PS reboot via FSBLReboot possible over FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button)

Note: Reset Status is visible on LEDs, see LED section

Boot Mode

S5-1S5-2Description
ONONDefault, boot from SD/microSD or SPI Flash if no SD is detected
OFFONBoot from eMMC
ONOFFBoot mode  PJTAG0
OFFOFFBoot mode main  JTAG

Note: Boot Mode Status is visible on LEDs, see LED section

UART

XMOD_TXD is sourced by MIO43 and MIO42 by XMOD_RXD.

Module SI5345

Module U5 Selection Pins are constant zero.

SD Card

SD Card selection is done via Micro SD Card detection.

SD WP is forwarded to ZynqMP from Master CPLD.

RGPIO

RGPIO Pin to FPGAValue
0SW1
1SW2
2XMOD_BTN
3Force FSBL reboot done
4SD_CD_S
5SD_CD_B
6Error
7ERR_STAT
11-8Boot Mode
12PG_LPD
13PG_DDR
14PG_FPD
15PG_PSGT
16PG_GT_L
17PG_GT_R
18POK_FMC
19DET_POWROK
20PWROK
21PG_PL
22PG_PLL
23PLL_LOL
24-27reserved
28-31Interface detection


RGPIO Pin from FPGAValue
0PLL_RSTn
1PERSTn
2FMC_FAN_EN
7LED_N
8LED_P
9HDLED_N
10HDLED_P
12-23unused
24-27reserved
28-31Interface detection

 

LED

LED2 D6 Green (near FAN1 connector on PCB)
 Power FlagsBlink SequenceComment
PWROK********ATX Power failed or PCB is powered off
PG_LPD*****oooModule Low Power Domain failed
PG_FPD****ooooModule Full Power Domain failed
PG_PL***oooooModule PL Power Domain failed
POK_1V8 or  POK_FMC**ooooooCarrier 1V8 or FMC VADJ Power Domain failed
PG_DDR='0' or PG_GT_L='0' or PG_GT_R='0' or PG_PSGT='0' or PG_PLL='0'*oooooooModule DDR, PL GT, PS GT or PLL Power Domain failed

OFFAll Ready


LED3 D7 Red (near FAN1 connector on PCB)
Bode ModeBlink SequenceComment
Error********ERROR
JTAG*****oooJTAG
PJTAG0****ooooBoot Mode is set to PJTAG0
eMMC***oooooBoot Mode is set to eMMC
SPI Boot**ooooooBoot Mode is set to QSPI
SD Boot*oooooooBoot Mode is set to SD

ONReset is on


XMOD LED  Red (XMOD1 on J12 with green dot)
StatusBlink SequenceComment
PS_INIT_B********

Indicates the PS is not initialized after a power-on reset (POR).

PS_ERROR_OUT*****ooo

The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU.

DONEON or OFF

Indicates the PL configuration is completed (LED is OFF).


LED_P/N (BLUE Power LED  on enclosure)
Status/ UserBlink SequenceComment
Power******** (slow blink)

Indicate board is powered off.

RGPIO controlledUser Defined

RGPIO 14 and 15, if RGPIO is active.

MIO40User Defined

MIO40, if RGPIO is deactivated


HDLED_P/N (Red HD LED  on enclosure)
Status/ UserBlink SequenceComment
PS_INIT_B********

Indicates the PS is initialized after a power-on reset (POR).

PS_ERROR_OUT*****ooo

The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU.

ERR_STAT****oooo

The PS_ERROR_STATUS indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status.

RGPIO controlledUser Defined

RGPIO 16 and 17, if RGPIO is active

SC0User DefinedSC0 (PL IO), if RGPIO is deactivated

Blink Frequency:

Blink SequenceComment
********~5,8 Hz
*****ooo~0,7 Hz, duty cycle 5/8
****oooo~0,7 Hz, duty cycle 4/8
***ooooo~0,7 Hz, duty cycle 3/8
**oooooo~0,7 Hz, duty cycle 2/8
*ooooooo~0,7 Hz, duty cycle 1/8

Appx. A: Change History

Revision Changes

CPLD REV05 to REV06

CPLD REV04 to REV05

Older Revision (PCB REV03) to CPLD REV04

Older Revision (PCB REV02) to CPLD REV04

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription


REV06REV02, REV03, REV04


  • typo correction
2017-11-15v.38REV06REV02, REV03, REV04John Hartfiel
  • Correction Boot Mode Section
2017-10-18

v.36

REV06REV02, REV03, REV04John Hartfiel
  • Revision 06 finished
2017-06-20

v.29

REV05REV02, REV03, REV04
John Hartfiel
  • description and style bug-fix
2017-06-09v.28REV05REV02, REV03, REV04
John Hartfiel
  • Revision 05 finished
2017-06-08v.23REV05REV02, REV03, REV04
John Hartfiel
  • Document style update
2017-05-08v.22REV05REV02, REV03, REV04
John Hartfiel
  • Revision 05 working in process
2017-02-08v.19REV04REV02, REV03, REV04 John Hartfiel
  • Revision 04 finished
2016-04-11

v.1

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  • Initial release
 All  

 

Appx. B: Legal Notices