Table of Contents
Download PDF version of this document. |
Table of Contents |
Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0725 for downloadable version of this manual and the rest of available documentation. |
The Trenz Electronic TE0725 is a low cost small-sized FPGA module integrating a Xilinx Artix-7 (15-100T) and 32 MByte Flash memory for configuration and operation.
Note that on the images below, there is no POF transceiver, 50-pin headers and JTAG/UART header installed.
Xilinx Artix-7 XC7A35T (A15 to A100T)
Commercial Temperature Grade (Industrial on Request)
32 MByte Flash Memory
2 x 50 Pin Headers with 2,54mm Pitch, Ideal for Breadboard Use
3.3V Single Power Supply with On-Board Voltage Regulators
Size 73 x 35 mm
JTAG/UART Connector
2 LED's
| Bank | VCCIO | B2B I/O | Notes |
|---|---|---|---|
| 0 | 3.3V | 0 | JTAG |
| 14 | 3.3V | 0 (3) | 3 I/O in XMOD-JTAG - for use as UART |
| 15 | 1.8V | 0 | used for optional hyper RAM |
| 16 | 2.5V | 0 | used for optional optical fiber transceiver |
| 34 | User select | 42 | 0R resistor option to select 3.3V |
| 35 | User select | 42 | 0R resistor option to select 3.3V |
| Model | Bitrate MB/s | Notes |
|---|---|---|
AFBR-59F2Z | 250 |
JTAG access to the Xilinx Artix-7 device is provided through connector JB1.
| Signal | Pin Number |
|---|---|
| TCK | JB1:4 |
| TDO | JB1:8 |
| TDI | JB1:10 |
| TMS | JB1:12 |
Connector JB1 (2 x 6 pin Header) is directly compatible to XMOD JTAG Adapter TE0790. This adapter can be inserted from top onto the TE0725, if JB1 is fitted with male pin header. Optionally JB1 can be fitted with pin header from bottom, in that case the JTAG cable connector must be on the base board.
When using XMOD-JTAG in JB1 then additionally USB UART is usable, and the push-button on XMOD works as configuration reset.
When using XMOD-JTAG please check the switch settings on XMOD to be sure the power and I/O reference are supplied correctly. TE0790 can be in some cases used to power up TE0725, however this is not recommended. TE0790-01 can not supply enough power for TE0725 (LED may blink but the module is not operating properly, especially in case of larger and more sophisticated designs).
| LED | Color | FPGA | Notes |
|---|---|---|---|
| D2 | Green | M16 | |
| D3 | Red | DONE | Active low |
All connectors are are for 100mil headers, all connector locations are in 100 mil grid.
| LED | Color | FPGA | Notes |
|---|---|---|---|
| D2 | Green | M16 | |
| D3 | Red | DONE | Active low |
To power-up a module, power supply with minimum current capability of 1A is recommended.
TE0725 needs one single power supply with nominal of 3.3V.
| FPGA | Design | Typical Power, 25C ambient |
|---|---|---|
| A35T | Not configured | TBD* |
| A35T | LED blinking | 170mW (typical) |
| A100T | Not configured | TBD* |
*TBD - To Be Determined.
Actual power consumption depends on the FPGA design and ambient temperature.
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
| Module Variant | FPGA Chip Model | PL Clock [MHz] | VIN Supply Voltage [V] | SPI Flash | HyperRAM |
|---|---|---|---|---|---|
TE0725-03-35-2C | XC7A35T-2CSG324C | 100 | 3.3V | S25FL256S | 8 MByte |
TE0725-03-100-2C | XC7A100T-2CSG324C | 100 | 3.3V | S25FL256S | 8 MByte |
TE0725-03-100-2I9 | XC7A100T-2CSG324I | 100 | 3.3V | S25FL256S | 8 MByte |
Parameter | Min | Max | Units | Notes | Reference document |
|---|---|---|---|---|---|
VIN supply voltage | -0.1 | 3.6 | V | ||
| I/O Bank supply voltage | -0.5 | 3.6 | V | Xilinx document DS181 | |
| I/O input voltage for FPGA I/O banks | -0.4 | VCCO_X+0.55 | V | Xilinx document DS181 | |
| GT Transceiver | -0.5 | 1.26 | V | Xilinx document DS181 | |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 1.8V or 3.3V nominal | Xilinx document DS181 |
Storage Temperature | -40 | +85 | °C |
| Parameter | Min | Max | Units | Notes | Reference document |
|---|---|---|---|---|---|
| VIN supply voltage | 3.135 | 3.45 | V | ||
| IO Bank supply voltage for I/O banks | 1.14 | 3.465 | V | Xilinx document DS181 | |
| I/O input voltage for I/O banks | -0.20 | VCCO + 0.20 | V | Xilinx document DS181 | |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | For assembly variant with 3.3V CONFIG Bank Option | Xilinx document DS181 |
| Please check Xilinx datasheet for complete list of absolute maximum and recommended operating ratings for the Artix-7 device (DS181). |
Please note that two different units are used on the figures below, SI system millimeter(mm) and imperial system thousandth of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mil's to millimeters and vice versa use formula 100mil's = 2,54mm.
All 100 mil pin headers are in 100 mil grid, the M3 mounting holes are in 50 mil grid aligned to the centers of the 100mil headers. The module is symmetrical, turning it 180 degrees will keep all I/O and Power pins in both 50 pin headers in compatible places.
Commercial grade modules
All parts conform to at least commercial temperature range of 0°C to +70°C.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C.
The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
| Weight g | Note |
|---|---|
| 8.5 | Plain Module |
| Date | Revision | Notes | PCN | Documentation link |
|---|---|---|---|---|
| 2016-12-09 | 03 | Second production release | Click to see PCN | TE0725 |
| - | 02 | First production release | TRM-TE0725-02 | |
| - | 01 | Prototypes |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-01-12 | REV03 product images added. | ||
| 2016-12-15 |
| Hardware REV03 specific information added | |
| 2016-12-09 | V40 | Hardware REV02 Block Diagram added | |
| 2016-12-02 | V1
| Initial version |