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Download PDF version of this document.

Table of Contents

Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TEBB0714+TRM for the current online version of this manual and other available documentation.

The Trenz Electronic TEBB0714 is a Carrier Board for testing, evaluation and development purposes, especially for the Multi Gigabit Transceiver units of the TE0714 module. Although this base-board is dedicated to the TE0714 module, it is also compatible with other Trenz Electronic 4 x 3 cm SoMs. See page "4 x 3 cm carriers" to get information about the SoMs supported by the TEBB0714 Carrier Board.

This base-board provides also through hole pads for pin headers to get access to the PL I/O-bank pins and further interfaces of the mounted TE 4 x 3 SoM.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEBB0714-01 Block Diagram.

Main Components

Figure 2TEBB0714-01 Carrier Board.

  1. 6-pin header J26 for selecting PL-bank I/O voltage
  2. 6-pin header J27 for selecting XMOD/JTAG VCCIO
  3. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  4. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  5. XMOD header, JX1
  6. Ultra small SMT coaxial connector, J5
  7. Ultra small SMT coaxial connector, J6
  8. Ultra small SMT coaxial connector, J7
  9. Ultra small SMT coaxial connector, J8
  10. User LED D1 (green)
  11. User LED D2 (red)
  12. LED D3 (red) indicating FPGA's 'Programming DONE'-signal
  13. SFP+ Connector, J1
  14. 10-pin header solder pads J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
  15. 16-pin header solder pads J3, JTAG/UART header with ADC and MGT clock input
  16. 50-pin header solder pads J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
  17. 50-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)

Initial Delivery State

Board is shipped in following configuration:

Different delivery configurations are available upon request.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connector

With the TEBB0714 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as differential pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and differential pairs of the B2B connectors JB1, JB2 and JB3:

B2B ConnectorInterfacesCount of I/O'sNotes
JM1User I/O54 single ended or 27 differential-
MGT lanes4 differential pairs, 2 lanes-
MGT reference clock input1-
JTAG4-
SoM control signals2'PROG_B', 'DONE'
ADC interface1 differential pair-
JM2User I/O36 single ended or 18 differential-
SFP+ Interface control signals8-
QSPI interface6-
UART interface2-
User LEDs2Red, Green
SoM control signals1'BOOTMODE'

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

On-board Pin Header

The TEBB0714 Carrier Board has 4 footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these pin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as  differential pairs.

Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

On-board Pin Header
Control Signals and InterfacesCount of I/O'sNotes
J17User I/O36 single ended or 18 differential-
QSPI interface6-
J20

User I/O

42 single ended or 21 differential-
J3JTAG4-
UART2-
SoM control signals2'BOOTMODE', 'PROG_B'
ADC1 differential pair-
MGT reference clock input1 differential pairAC decoupled on-board (100 nF capacitor)
JX1JTAG4-
UART2-
SoM control signals2'BOOTMODE', 'PROG_B'
J4User I/O6 single ended or 3 differential3.3V, 3.3V_OUT voltage level available on header

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

SFP+ Connector

The TEBB0714 Carrier Board is equipped with one SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).

The differential RX/TX data lanes are connected to B2B connector JM1, the control-lines are connected to B2B connector JM2.

Following table describes the pin-assignment of the SFP+ connector in detail:

SFP+ pinPin Schematic NameB2BFPGA DirectionDescriptionNote
Transmit Data + (pin 18)MGT_TX2_PJM1-14OutputSFP+ transmit data differential pair

-
Transmit Data - (pin 19)MGT_TX2_NJM2-16Output-
Receive Data + (pin 13)MGT_RX2_PJM1-7InputSFP+ receive data differential pair

-
Receive Data - (pin 12)MGT_RX2_NJM1-9Input-
Receive Fault (pin 2)SFP0_TX_FAULTJM2-42InputFault / Normal OperationHigh active logic
Receive disable (pin 3)SFP0_TX_DISJM2-44OutputSFP Enabled / DisabledLow active logic
MOD-DEF2 (pin 4)SFP0_SDAJM2-46BiDir2-wire Serial Interface data3.3V pull-up on-board
MOD-DEF1 (pin 5)SFP0_SCLJM2-48Output2-wire Serial Interface clock3.3V pull-up on-board
MOD-DEF0 (pin 6)SFP0_M-DEF0JM2-40InputModule present / not presentLow active logic
RS0 (pin 7)SFP0_RS0JM2-38OutputFull RX bandwidthLow active logic
LOS (pin 8)SFP0_LOSJM2-34InputLoss of receiver signalHigh active logic
RS1 (pin 9)SFP0_RS1JM2-32OutputReduced RX bandwidthLow active logic

Table 3: SFP+ connector pin-assignment.

Ultra Small SMT Coaxial Connectors

4 HIROSE Ultra Small Surface Mount Coaxial Connectors (up to 6 Gbit/s transmission rate) are present on the Carrier Board available for access to one MGT lane of the SoM. The connectors have the manufacturer designation 'U.FL-R-SMT-1', mating hight: 2.4 mm.

Each conductor of the RX and TX differential pair is routed to one coaxial connector:

Connector DesignatorConnected toB2B Connector
J5MGT_TX3_PJM1-8
J6MGT_TX3_NJM1-10
J7MGT_RX3_PJM1-1
J8MGT_RX3_NJM1-3

Table 4: Pin-assignment of the coaxial connectors.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1 and pin header J3. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.

JTAG Signal

B2B Connector Pin

XMOD Header JX1Pin Header J3Note
TCKJM1-90JX1-4J3-4-
TDIJM1-86JX1-10J3-10-
TDOJM1-88JX1-8J3-8-
TMSJM1-92JX1-12J3-12-

Table 5: JTAG interface signals.

XMOD FTDI JTAG-Adapter Header JX1

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1, so in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1:

Pin Schematic NameXMOD Header JX1 PinB2BNote
TCKC (pin 4)JM1-90-
TDOD (pin 8)JM1-88-
TDIF (pin 10)JM1-86-
TMSH (pin 12)JM1-92-
B14_L25A (pin 3)JM2-97UART (output from module to XMOD Programmer)
B14_L0B (pin 7)JM2-99UART (input to module from XMOD Programmer)
BOOTMODEE (pin 9)JM2-100-
PROG_BG (pin 11)JM1-94-

Table 6: XMOD header JX1 signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board's and module's 3.3V supply voltage. Set the XMOD DIP-switch with the setting:

XMOD DIP-switchesPosition
Switch 1ON
Switch 2OFF
Switch 3OFF
Switch 4

OFF

Table 7: XMOD adapter board DIP-switch positions for voltage configuration.


The I/O-voltage of the XMOD adapter board with the schematic name 'V_CFG' and pin-name 'VIO' (pin 6) on XMOD header JX1 can be selected via Jumper J27:

V_CFG Value

Jumper J27 SettingNote
1.8Vpins 1-2 connectedModule's output voltage.
V_CFG0*pins 3-4 connectedInternal module VCCIO: 3.3V or 1.8V (Settable by 0-Ohm-Resistor on TE0714 module).
3.3V_OUTpins 5-6 connectedModule's output voltage.

*Default setting, do not changed, if V_CFG0 Bank power is sourced by module itself.

Table 8: Setting of reference I/O-voltage XMOD header.


Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

JTAG/UART Header J3

As alternative to the XMOD header JX1, on the Carrier Board pin header J3 is present with 4 additional pins as differential pairs to supply the mounted SoM with an external MGT reference clock signal and to provide differential analog signal input:

Pin Schematic NameHeader J3 PinB2BNote
TCK4JM1-90-
TDO8JM1-88-
TDI10JM1-86-
TMS12JM1-92-
B14_L253JM2-97UART (output from module)
B14_L07JM2-99UART (input to module)
BOOTMODE9JM2-100-
PROG_B11JM1-94-
XADC_P13JM1-25Analog input differential pair
XADC_N14JM1-27
CLK0_N15JM1-4AC decoupled on-board (100 nF capacitor)
CLK0_P16JM1-2

Table 9: JTAG/UART header J3 signals and connections.

UART Interface

UART interface is available on B2B connector JM2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

UART Signal Schematic NameB2BXMOD Header JX1Pin Header J3Note
B14_L0JM2-99JX1-7J3-7UART (input to module)
B14_L25JM2-97JX1-3J3-3UART (output from module)

Table 10: UART interface signals.

QSPI Interface

The QSPI interface (if available) of the mounted SoM is routed to the pin header J17. The reference I/O-voltage of the module have to be noticed when using this interface.

SD IO Signal Schematic NameB2BPin Header J17Note
SPI-DQOJM2-68J17-24QSPI data
SPI-DQ1JM2-71J17-27QSPI data
SPI-DQ2JM2-73J17-28QSPI data
SPI-DQ3JM2-70J17-23QSPI data
SPI-CLKJM2-67J17-26QSPI clock
SPI_CSJM2-69J17-25QSPI chip select

Table 11: QSPI interface signals.

On-board Peripherals

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On-board LEDs

The on-board LEDs are available to the user and can be used to indicate system status and activities:

LED DesignatorColorPin Schematic NameB2B ConnectorIndicating
D1greenGLEDJM2-26Available to user.
D2redRLEDJM2-24Available to user.
D3redDONEJM1-96FPGA module programmed properly.

Figure 12: On-board LEDs

VCCIO Selection Jumper

On the TEBB0714 Carrier Board the PL-bank I/O voltage (schematic name 'VCCIO34') can be selected by the jumper J26.

VCCIO34 Value

Jumper J26 SettingNote
1.8Vpins 1-2 connectedModule's output voltage.
2.5Vpins 3-4 connectedVoltage generated by on-board LDO U1.
3.3V_OUTpins 5-6 connectedModule's output voltage.

Table 13: Base-board PL-bank I/O voltage setting.

Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 3 module to avoid failures and damages to the functionality of the mounted SoM.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
3.3VTBD*

Table 14: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence.

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

The external power-supply can be connected to the board by the following pins:

Connector3.3V pinGND pin
JX1

JX1-5, JX1-6,

JX1-1, JX1-2
J3J3-5, J3-6J3-1, J3-2
J4J4-5J4-1, J4-2
J20J20-5, J20-46J20-1 , J20-2 , J20-49 , J20-50
J17J17-5, J17-46J17-1 , J17-2 , J17-49 , J17-50

Table 15: Connector pins capable for external 3.3V power supply

Power Distribution Dependencies

The PL-bank I/O voltages 1.8V, 2.5V and 3.3V will be available after the mounted SoM's 3.3V voltage level has reached stable state on B2B-connector pins JM1-83 and JM2-54, meaning that all on-module voltages have become stable and module is properly powered up.

Following diagram shows the distribution of the external input voltage of nominal 3.3V to the components:


Figure 3: Board power distribution diagram.

Power Rails

The voltage direction of the power rails is from board and on-board connectors' view:

Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
JM1

3.3V

Out

97, 99

3.3V module supply voltage
3.3V_OUTIn833.3V module output voltage
VCCIO34Out61PL IO-bank VCCIO
JM2

1.8V

In

18

1.8V module output voltage
3.3V_OUTOut543.3V module output voltage
V_CFG0In/out53Direction depends on solder option of the modul: Internal module VCCIO 3.3V or 1.8V or source from carrier is possible

Table 16: Power pin description of B2B module connector.


On-board Pin Header DesignatorVCC / VCCIODirectionPinsNotes
J17

3.3V

In / Out

5, 46

3.3V external supply voltage
V_CFGOut / int6, 45direction depends on jumper 27 settings and module solder option
J20

3.3V

In / Out

5, 46

3.3V external supply voltage
VCCIO34In / Out6, 45PL IO-bank VCCIO, depends on Jumper settings

Table 17: Power Pin description of on-board connector.


Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J26VCCIO34In1, 3, 5-
1.8VOut2-
2.5VOut4-
3.3V_OUTOut6-
J27V_CFGIn / Out1, 3, 5direction depends on jumper 27 settings and module solder option
1.8VOut2-
V_CFG0Out4-
3.3V_OUTOut6-

Table 18: Power Pin description of VCCIO selection jumper pin header.


JTAG/UART Header DesignatorVCC / VCCIODirectionPinsNotes
JX1 (XMOD)3.3VOut5Connected to 3.3V external supply voltage
VIOOut6Connected to 'V_CFG', depends on jumper 27 settings
J33.3VOut5Connected to 3.3V external supply voltage
V_CFGOut6direction depends on jumper 27 settings and module solder option

Table 19: Power pin description of XMOD/JTAG Connector.

Board to Board Connector

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsNotes

Vin supply voltage

3.135

3.465

V

3.3V supply-voltage ± 5%

Storage Temperature

-4085

°C

WL-SMCW SMD chip LED data sheet

Table 20: Absolute maximum ratings.

Recommended Operating Conditions

 ParameterMinMaxUnitsNotes
Vin supply voltage3.1353.465V-
Operating temperature-40+85°CMolex 74441-0001 Product Specification

Table 21: Recommended operating conditions.

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

The Carrier Board is operable within industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

 The dimensions are given in mm and mil (milli inch).

Figure 4: Board physical dimensions drawing.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

  • First Production Release
-TEBB0714-01

Table 22: Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure 5: Board hardware revision number.

Document Change History

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Date

Revision

Contributors

Description

Ali Naseri, Jan Kumann
  • First TRM release

Table 23: Document change history.

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