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Table of Contents |
Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/carrier_boards/TE0703 for downloadable version of this manual and the rest of available documentation. |
The Trenz Electronic TE0703 Carrier Board is a base-board for 4x5 SoM's, which exposes the MIO- and the PS/PL-pins of the SoM to accessible connectors and provides a whole range of on-board-components to test and evaluate Trenz Electronic 4x5 SoM's.
See page "4 x 5 cm carriers" to get information about the SoM's supported by the TE0703 Carrier Board.
Board is shipped in following configuration:
Switch | Position | Description |
---|---|---|
S2-1 | ON | Mode control MC1. |
S2-2 | ON | Mode control MC0. |
S2-3 | ON | JTAG enabled for B2B JB1 connector. |
S2-4 | OFF | Boot mode set to QSPI. |
Different delivery configurations are available upon request.
For detailed information about the B2B pin out, please refer to the Master Pin-out Table.
Micro SD Card socket is not directly wired to the B2B connector pins, but through a Texas Instruments TXS02612 SDIO port expander, which is needed for voltage translation due to the different voltage levels of the Micro SD Card and MIO bank 501 of the Xilinx Zynq 7000 chip. The Micro SD Card has 3.3 V signalling, but the MIO Bank 501 on the Xilinx Zynq 7000 chip is set to 1.8 V.
TE0703 has on-board USB 2.0 High Speed UART/FIFO FT2232HQ from FTDI. Channel A can only be used in simple UART mode, Channel B can be used as UART, FIFO, JTAG (MPSSE) or High Speed Serial modes. An standard 256 Byte EEPROM to store custom Configuration settings for FT2232H is available. EEPROM settings can be changed using FTDI provided tools that can be downloaded from FTDI website. See FTDI website for more information.
On-board ethernet jack J14 pins are routed to B2B connector JB1. Ethernet jack J14 LED's are all routed to CPLD Bank 1.
TE0703 board has two physical USB sockets:
JTAG access to the CPLD and Xilinx Zynq chip on the SoM is provided via Mini-USB JTAG Interface (FTDI FT2232H) and controlled by DIP switch S2-3. JTAG pins are routed from CPLD to the JB2 connector as follows:
JTAG Signal | B2B JB2 Connector Pin |
---|---|
TCK | JB2-100 |
TDO | JB2-98 |
TDI | JB2-96 |
TMS | JB2-94 |
There are four LED's on-board:
LED | Color | Description |
---|---|---|
D1 | Red | FTDI UART receive activity |
D2 | Green | FTDI UART transmit activity |
D3 | Red | CPLD signal FL_0 |
D4 | Green | CPLD signal FL_1 |
LED's D3 and D4 are also connected to the B2B connector JB2 pins FLED1 and FLED2 respectively and can be controlled by 4x5 SoM FPGA module.
Switch | ON | OFF | Notes |
---|---|---|---|
S2-1 | User configurable, routed to CPLD | User configurable, routed to CPLD | |
S2-2 | User configurable, routed to CPLD | User configurable, routed to CPLD | |
S2-3 | JTAG enabled for B2B connector JB2 | JTAG enabled for CPLD | |
S2-4 | Boot from SD Card | Boot from QSPI flash on module | Used as CARD Detect - as the SD card connector has no CD pin |
Power supply with minimum current capability of 3A for system startup is recommended.
TE0703 needs one single power supply with nominal of 5V.
Power Input Pin | Max Current |
---|---|
VIN | 4A |
Typical power consumption for TE0703-05 + TE0715-01 module with SD micro card inserted, ethernet connected, link up, system booted into Linux prompt and idling is 5V / 0.55A.
It is not allowed to feed any voltage to any external I/O pin before there is no power indication on M3.3VOUT pins. Presence of 3.3V on B2B JB2 connector pins 9 and 11 indicates that module is properly powered up and ready.
If any of the VCCIOA, VCCIOB, VCCIOC or VCCIOD will be powered through external connectors J1 or J2, then corresponding VCCIO jumper should also be removed altogether, see next chapter.
Refer to the 4x5 Module Integration Guide for VCCIO voltages options.
Jumper J5 | 1-2 | 2-3 | Voltage |
---|---|---|---|
VCCIOA | ON | OFF | 1.8 V |
VCCIOA | OFF | ON | 3.3 V |
Jumper J8 | 1-2 | 2-3 | Voltage |
---|---|---|---|
VCCIOB | ON | OFF | 1.8 V |
VCCIOB | OFF | ON | 3.3 V |
Jumper J9 | 1-2 | 2-3 | Voltage |
---|---|---|---|
VCCIOC | ON | OFF | 1.8 V |
VCCIOC | OFF | ON | 3.3 V |
Jumper J10 | 1-2 | 2-3 | Voltage |
---|---|---|---|
VCCIOD | ON | OFF | 1.8 V |
VCCIOD | OFF | ON | 3.3 V |
Parameter | Min | Max | Units | Reference document |
---|---|---|---|---|
Supply Voltage VCC | -0.33 | 5.5 | V | |
Operating temperature | -40 | +125 | °C | MachXO2 Family Datasheet |
Storage temperature | -55 | +125 | °C |
Parameter | Min | Max | Units | Reference document |
---|---|---|---|---|
Supply Voltage VCC | 4.75 | 5.25 | V | |
Operating temperature | 0 | +70 | °C |
Assembly variants for higher storage temperature range are available on request. |
Please check components datasheets for complete list of absolute maximum and recommended operating ratings. |
Board size: PCB 100mm × 64.5mm. Notice that the mini USB-B jack on the left and ethernet RJ-45 jack on the right are hanging slightly over the edge of the PCB making the total width of the longer side approximately 106mm. Please download the assembly diagram for exact numbers.
Mating height of the module with standard connectors: 8mm
PCB thickness: 1.65mm
Highest parts on the PCB are USB type A jack and ethernet RJ-45 jack, approximately 15mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.
42g - Plain board
13g - VG96 connector x 2
Date | Revision | Notes | PCN | Documents |
---|---|---|---|---|
2016-09-07 | 05 | Added VCCIO Jumpers | TE0703 | |
- | 04 | Corrected FTDI EEPROM connection | - | TE0703-04 |
- | 03 | Added VCCIO strapping resistors | - | |
- | 02 | First series boards | - | |
- | 01 | Prototypes | - |
Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Date | Revision | Contributors | Description |
---|---|---|---|
2017-02-02 | Jan Kumann | New board image with silk screen pin markings for VG96 connectors J1 and J2. | |
2016-12-22 | V14 | Jan Kumann | Block diagram added. |
2016-12-08 | V10 | Jan Kumann | Document structure revised. |
2016-12-05 | V5 | John Hartfiel | Corrected Boot Mode table. |
2016-09-06 | V1 | Jan Kumann, John Hartfiel | Initial document. |