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Trenz Electronic TE0713 is an industrial-grade FPGA module integrating Xilinx Artix-7 FPGA, USB 3.0, 1 GByte of DDR3 SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Block Diagram

Main Components

  1. Xilinx Artix-7 XC7A series FPGA, U1
  2. ...
  3. ...
  4. System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3
  5. ...

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Programmable unit



Xilinx Artix-7 FPGANot programmedU1
System Controller CPLDProgrammedU3
SPI Flash OTP areaEmptyU4

SPI Flash main array

SPI Flash Quad Enable bitSetU4

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA banks and I/O signals connected to the B2B connectors:

FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM114VCCIO13Supplied by the baseboard.
13JM218VCCIO13Supplied by the baseboard.
13JM32VCCIO13Supplied by the baseboard.
15JM248VCCIO15Supplied by the baseboard.
15JM22VCCIO15Supplied by the baseboard.
16JM148VCCIO16Supplied by the baseboard.

JTAG Interface

JTAG access to the Xilinx Artix-7 FPGA and System Controller CPLD devices is provided through B2B connector JM2.

JTAG Signal

B2B Pin


JTAGEN pin in B2B connector JM1 is used to select JTAG access for FPGA or SC CPLD:

LowArtix-7 FPGA
HighSystem Controller CPLD

System Controller I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
PGOODOutputPower goodActive high when all on-module power supplies are working properly.
JTAGENInputJTAG selectLow for normal operation, high for System Controller CPLD access.
EN1InputPower EnableWhen forced low, pulls POR_B low to emulate power on reset.
NOSEQ-No functionNot used.
MODE-No functionNot used.


The TE0713-01 module has one LED which is connected to the System Controller CPLD. Once FPGA configuration has completed, it can be used by the user's design. 

LEDColorSC SignalSC PinNotes
D1GreenSYSLED18Exact function is defined by SC CPLD firmware.


Si5338 programmable clock generator chip is used to generate clocks with 25 MHz oscillator as input connected to the pin IN3. There is a I2C bus connected between the FPGA bank 14 (master) and clock generator chip (slave) which can be used to program output frequencies. See the reference design for more information.

System Controller CPLD

System Controller CPLD (Lattice MachXO2-256HC, U3) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.

By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s baseboard PCB via the B2B connector JM2 pin 18.

Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1 low, on-board DC-DC converters will be not turned off.

User can create their own System Controller design using Lattice Diamond software. Once created it can be programmed into CPLD via JTAG interface.


The TE0713-01 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application code and data.

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Power and Power-On Sequence

Power Supply

Single 3.3V power supply (for both VIN and 3.3VIN power rails) with minimum current capability of 3A for system startup is recommended.

Power Consumption

Typical module power consumption is between 2-3W. Exact power consumption is to be determined.

TE0713-01 module can also be powered by split 5V/3.3V power sources if preferred. In such case apply 5V to B2B connectors VIN pins and 3.3V to 3.3VIN pins, although lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 5V/3.3V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises).

Power-On Sequence

For the highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0713 module.

Power Rails

Power Rail Name

B2B Connector JM1 Pin

B2B Connector JM2 Pin




1, 3, 52, 4, 6, 8InputSoM supply voltage (from the baseboard).
3.3VIN13, 15-InputSoM supply voltage (from the baseboard).
DDR_PWR-19OutputModule internal 1.35V level.



Module internal 1.8V level. Maximum 300mA available.

3.3V-10, 12OutputModule internal 3.3V level.
VCCIO13-1, 3Input

High-Range bank supply voltage (from the baseboard).

VCCIO15-7, 9InputHigh-Range bank supply voltage (from the baseboard).
VCCIO169, 11-InputHigh-Range bank supply voltage (from the baseboard).
VREF_JTAG-91OutputJTAG reference voltage (3.3V).

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings




Reference Document

VIN supply voltage



3.3VIN supply voltage  V 

Storage temperature (ambient)




See IM4G16D3FABG datasheet.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage  V 
3.3VIN supply voltage  V 
Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

All dimensions are shown in millimeters.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.


21 g Plain module.

8.8 g Set of nuts and bolts.

Revision History

Hardware Revision History



PCNDocumentation Link


First production revision


Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History





Jan KumannInitial document.