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Trenz Electronic TE0713 is an industrial-grade FPGA module integrating Xilinx Artix-7 FPGA, USB 3.0 to FIFO bridge, 1 GByte of DDR3L SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components


  1. Xilinx Artix-7 XC7A series FPGA, U1
  2. 32 MByte QSPI Flash memory, U4
  3. 30.000 MHz quartz crystal, Y1
  4. System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3
  5. Green LED (SYSLED1), D1
  6. 4 Gbit DDR3L 256M x 16 SDRAM, U15
  7. Altera Enpirion 12A PowerSoC DC-DC converter, U14
  8. Silicon Labs programmable quad clock generator, U2
  9. SiTime low-power programmable oscillator @ 25.000000 MHz, U9
  10. 4 Gbit DDR3L 256M x 16 SDRAM, U19
  11. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  12. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  13. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  14. FTDI USB 3.0 to FIFO interface bridge, U11
  15. Texas Instruments 3A step-down converter (DDR_PWR), U7
  16. Texas Instruments 3A step-down converter (1.8V), U5
  17. Texas Instruments 3A step-down converter (1.2V_MGT), U8
  18. Texas Instruments 3A step-down converter (1V_MGT), U6
  19. Texas Instruments PFET load switch, Q1

Initial Delivery State

Programmable unit



Xilinx Artix-7 FPGANot programmedU1
System Controller CPLDProgrammedU3
SPI Flash OTP areaEmptyU4

SPI Flash main array

SPI Flash Quad Enable bitSetU4

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA banks and I/O signals connected to the B2B connectors:

FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM114VCCIO13Supplied by the baseboard.
13JM218VCCIO13Supplied by the baseboard.
13JM32VCCIO13Supplied by the baseboard.
15JM248VCCIO15Supplied by the baseboard.
15JM22VCCIO15Supplied by the baseboard.
16JM148VCCIO16Supplied by the baseboard.

JTAG Interface

JTAG access to the Xilinx Artix-7 FPGA and System Controller CPLD devices is provided through B2B connector JM2.

JTAG Signal

B2B Pin


JTAGEN pin in B2B connector JM1 is used to select JTAG access for FPGA or System Controller CPLD:

LowArtix-7 FPGA
HighSystem Controller CPLD

System Controller I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
PGOODOutputPower goodPower Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).
JTAGENInputJTAG selectLow for normal operation, high for System Controller CPLD access.
EN1InputPower EnableWhen forced low, pulls PROG_B low to emulate power on reset.

When forced low, pulls PROG_B low to emulate power on reset.
NOSEQ-No functionNot used.
MODE-No functionNot used.

Note: Pin functionality depends on the running CPLD Firmware, newest one is described here TE0713 CPLD

On-board LEDs

The TE0713-01 module has one LED which is connected to the System Controller CPLD. Once FPGA configuration has completed, it can be used by the user's design. 

LEDColorSC SignalSC PinNotes
D1GreenSYSLED18Exact function is defined by SC CPLD firmware.


On-board Si5338 clock generator chip is used to generate clocks with 25 MHz oscillator connected to the pin IN3 as input reference. There is a I2C bus connection between the FPGA bank 14 (master) and clock generator chip (slave) which can be used to program output frequencies. See the reference design for more information.

CLK OutputFPGA BankFPGA PinIO StandardNet NameDefault FreqNote
CLK0 ------N.C.
CLK1-- ----


CLK2216F6/E6AutoMGT_CLK0_P/N125 MHzGTP transceiver clock.

AC coupled, board termination

On-board Peripherals

32 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

System Controller CPLD

System Controller CPLD (Lattice Semiconductor MachXO2-256HC, U3) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.

CPLD Firmware description:


The TE0713-01 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application code and data.

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

USB 3.0 to FIFO Bridge

TE0713-01 is equipped with the FTDI FT600Q high performance USB 3.0-to-FIFO interface bridge chip.

FTDI doesn't support 245 Synchronous FIFO mode on TE0713, please use FT60X Chip Configuration Programmer to change Mode into  “Multi-Channel FIFO mode”.

SSTX_P and SSTX_N ar swapped on the PCB,this will be corrected automatically on link training on USB3

Power and Power-On Sequence

Power Supply

Single 3.3V power supply (for both VIN and 3.3VIN power rails) with minimum current capability of 3A for system startup is recommended.

Power Consumption

Typical module power consumption is between 2-3W. Exact power consumption is to be determined.

TE0713-01 module can also be powered by split 5V/3.3V power sources if preferred. In such case apply 5V to B2B connectors VIN pins and 3.3V to 3.3VIN pins, although lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 5V/3.3V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises).

Power-On Sequence

For the highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0713 module.

Power Rails

Power Rail Name

B2B Connector JM1 Pin

B2B Connector JM2 Pin




1, 3, 52, 4, 6, 8InputSoM supply voltage (from the baseboard).
3.3VIN13, 15-InputSoM supply voltage (from the baseboard).
DDR_PWR-19OutputModule internal supply of 1.35V level.
1V---Module internal supply of 1V level.
1V_MGT---Module internal supply of 1V for bank 216 transceivers.
1.2V_MGT---Module internal supply of 1.2V for bank 216 transceivers.



Module internal 1.8V level. Maximum 300mA available.

3.3V-10, 12OutputModule internal 3.3V level.
VCCIO13-1, 3Input

High-Range bank supply voltage (from the baseboard).

VCCIO15-7, 9InputHigh-Range bank supply voltage (from the baseboard).
VCCIO169, 11-InputHigh-Range bank supply voltage (from the baseboard).
VREF_JTAG-91OutputJTAG reference voltage (3.3V).

Board to Board Connectors

Variants Currently In Production

Module Variant


Junction Temperature

Temperature Range
TE0713-01-100-2CXC7A100T-2FGG484C0°C to 85°CCommercial grade
TE0713-01-200-2CXC7A200T-2FBG484C0°C to 85°CCommercial grade

Technical Specifications

Absolute Maximum Ratings




Reference Document

VIN supply voltage



See EN63A0QI and TPS82085 datasheets.
3.3VIN supply voltage-0.53.75VSee LCMXO2-256HC datasheet.
HR I/O banks supply voltage (VCCO)-0.53.6
VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181

Storage temperature




See IM4G16D3FABG datasheet.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage2.56.0VSee TPS82085 datasheet.
3.3VIN supply voltage2.3753.6VSee LCMXO2-256HC datasheet.
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.2VXilinx datasheet DS181

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

All dimensions are shown in millimeters.



21 g Plain module.

8.8 g Set of nuts and bolts.

Revision History

Hardware Revision History



PCNDocumentation Link


First production revision


Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History





  • Note USB3
2019-07-03v.13John Hartfiel
  • History bugfix
  • Correction of System Controller IO description
2018-10-24v.11John Hartfiel
  • Note USB3


v.9John Hartfiel
  • add default SI5338 clk table


v.8John Hartfiel
  • replace B2B connector section
2017-05-28v.6Jan Kumann
  • Absolute and recommended ratings added.
  • Main components section improved. New top PCB image.
  • Power rails section improved.
  • New physical dimensions images.


Jan Kumann
  • Initial document.

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