Overview

Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/carrier_boards/TEBB0714 for downloadable version of this manual and additional technical documentation of the product.

The Trenz Electronic TEBB0714 is a base-board for test- and evaluation-purposes, especially for the Multi-gigabit transceiver units of the TE0714 module. Although this base-board is dedicated to the TE0714 module, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs. See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEBB0714 base-board.

This base-board provides also soldering-pads as place-holders for pin-headers as option to get access to the PL-IO-banks of the mounted SoM.

Block Diagram

Figure 1: TEBB0714 -01 Block Diagram

Main Components

Figure 2: 4 x 5 cm SoM carrier board TEBB0714-01

TEBB0714 -01:

1. 6-pin header J26 for selecting Bank34 VCCIO voltage
2. 6-pin header J27 for selecting XMOD/JTAG reference voltage
3. Samtec Razor Beam™ LSHM-150 B2B connector JM1
4. Samtec Razor Beam™ LSHM-150 B2B connector JM2
5. JTAG/UART header JX1 ('XMOD FTDI JTAG Adapter' compatible pin-assignment)
6. Ultra small SMT coaxial connector J5
7. Ultra small SMT coaxial connector J6
8. Ultra small SMT coaxial connector J7
9. Ultra small SMT coaxial connector J8
10. User LED D1 (green)
11. User LED D2 (red)
12. LED D3 (red) indicating 'Programming DONE'-signal from module's FPGA
13. SFP+ Connector J1
14. 10-pin header soldering-pads J4 for access to SoM's PL IO-banks (LVDS-pairs possible)
15. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter' compatible pin-assignment) with 4 additional pins for reference-clock input to 4 x 5 cm SoM and one LVDS-pair for analog signal input
16. 50-pin header soldering-pads J20 for access to SoM's PL IO-banks (LVDS-pairs possible)
17. 50-pin header soldering-pads J17 for access to SoM's PL IO-banks (LVDS-pairs possible)

Key Features

• SFP+ connector (Enhanced small form-factor pluggable), supports data transmission rates up to 10 Gbit/s
• 4 Hirose Ultra small SMT coaxial connectors, supports data transmission rates up to 6 Gbit/s
• TE 4 x 5 cm SoM programable by JTAG header (JX1)
• 2 x user LEDs routed to IO-pins of the SoM
• Soldering-pads J17 and J20 as place-holder for further possibilities to access to SoMs IO-bank-pins, usable as LVDS-pairs
• Soldering-pads J3 and J4 as place-holder for access to JTAG- or IO-ports of the SoM
  

Interfaces and Pins

SFP+ Connector

The TEBB0714 Carrier Board there provides a SFP+ connector J1 (Molex 74441-0001 at board-rev. 01 ). The connector is embedded into a SFP cage J2 (Molex 74737-0009 at board-rev. 01).

The RX-/TX-data-lanes are connected to B2B-connector JM1, the control-lines are connected to pins on B2B-connector JM2.

On this SFP+ connector, MGT-lane 2 is accessible at mounted 4 x 5 SoM TE0714.

The pin-assignment of the SFP connector is in detail as fellows:

Table 1: SFP+ connector pin-assignment

Ultra small SMT coaxial connector

........

.........

JTAG/UART Interface

The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1. This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment:

Table 3: JTAG header JX1 pin-assignment

There is also the option to mount and solder a 2-row 16-pin header to the place-holder J3, which has the same pin-assignment as header JX1, but with two additional two pins (15,16) as LVDS-pair to supply the mounted 4 x 5 SoM with an external reference clock-signal. The clock-signal is linked to to the SoM via B2B-connector pins JB2-32 (MGT_CLK0_N) and JB2-34 (MGT_CLK0_P).

Further two additional pins (13, 14) are designated as LVDS-pair for analog signals and routed to the ADC-unit of the SoM. This LVDS-pair has 1K serial resistors on both conductors and has on the B2B-connector JM1 the pins JM1-25 and JM1-27 with the net-names 'ADC_P' and 'ADC_N'.

On both interfaces (JX1, J3), the pins with the net-names B14_L25 and B14_L0 are available as user IO's which could be used as UART-interface for example.

LEDs

There are two LEDs D1 (green) and D2 (red) available to the user. The green LED D1 is connected to the B2B-connector pin JM2-26 with the net-name 'GLED', the red LED D2 is connected to the pin JM2-24 with the net name 'RLED'.

LED D3 (red) is linked to the SoM's output signal 'DONE' indicating that the FPGA-modul is programmed properly.

Header place-holder J4

The place-holder J4 with solder-pads to mount a 2-row 10-pin header provides additional 3 LVDS-pairs with the pin-mapping 3-4, 7-8 and 9-10. The LVDS-pairs are operable with the VCCIOs 3.3V or 3.3V_OUT from mounted module.

Header place-holder J17 and J20

The place-holders J17 and J20 with solder-pads to mount 2-row 50-pin headers provide the capability to access the PL IO-bank pins of the mounted 4 x 5 SoM.

With mounted header J20 there are 42 IO's of PL-IO-bank 34 of the 4 x 5 SoM available, which are also usable as 21 LVDS-pairs. On this header the IO's are operable with fixed 3.3V or selectable VCCIO-voltage VCCIO34.

On header J17 there are 36 IO's available of PL-IO-bank 14. This IO's are also usable as 18 LVDS-pairs and operable with fixed 3.3V or module's config-VCCIO V_CFG (depending on module's configuration: 3.3V or 1.8V). This header provides also a QSPI interface consisting of 6 IO's.

Power

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

The external power-supply can be connected to the board by the following pins:

Table 4: Connector-pins capable for external 3.3V power-supply

Power-On Sequence

The PL IO-bank supply-voltages 1.8V, 2.5V and 3.3V will be available after the mounted module's 3.3V voltage level is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

Note: The supply-voltages have low current dropout.

Figure 3: Power-On sequence diagram

Configuring VCCIO 

On the TEBB0714 carrier board different VCCIO configurations can be chosen by the jumper J26 and J27.

The purpose of the jumper of the Carrier Board will be explained in the following sections.

Summary of VCCIO-configuration

On the TEBB0714 carrier board the PL IO-bank's supply voltages of the 4x5 SoM (VCCIOA, VCCIOD; see 4x5 Module Integration Guide) are connected to the base-board VCCIO-voltage VCCIOA and VCCIOD, which are selectable between the supply-voltages 1.8V, 2.5V and 3.3V via jumper J26 and J27.

Table 5: base-board supply-voltages VCCIOA and VCCIOD

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

• Board size:  PCB 56.47 mm ×  75 mm. Notice that some parts the are hanging slightly over the edge of the PCB like the mini USB-jacks and the SFP+ connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• Mating height of the module with standard connectors: 8mm

• PCB thickness: ca. 1.65mm

• Highest part on the PCB is the SFP+ connector, which has an approximately 11.3 mm overall hight. Please download the step model for exact numbers.

 The dimensions are given in mm and mil (milli inch).

Figure 4: Physical Dimensions of the TEBA0841-01 carrier board

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

ca. 32 g - Plain board

Document Change History

date	revision	authors	description
2017-02-08		Ali Naseri	current TRM for TEBA0841-01
2017-01-30	0.1	Ali Naseri	Initial document

Hardware Revision History

Figure 5: Hardware revision Number

Hardware revision number is printed on the PCB board next to the model number separated by the dash.

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