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The Trenz Electronic TE0745 is an industrial-grade SoC module integrating a Xilinx Zynq-7 (Z-7030, Z-7035 or Z-7045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Figure 1: TE0745-02 Block Diagram
Figure 2: TE0745-02 SoC module
Industrial-grade Xilinx Zynq-7000 (Z-7030, Z-7035, Z-7045) SoM
Additional assembly options are available for cost or performance optimization upon request.
Storage device name | Content | Notes |
---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
Si5338 OTP NVM | Default settings pre programmed | OTP not reprogrammable after delivery from factory |
Table 1: Initial delivery state
The Board to Board connectors are high-speed hermaphroditic stacking strips and provide a modular interface to the SoC's PL and PS I/O's.
The connector supports single ended and differential signaling as the I/O's are usable as LVDS-pairs.
The I/O signals are routed from the SoC's PL banks as LVDS-pairs to the B2B connector.
Bank | Type | B2B Connector | I/O signal count | LVDS-pairs count | VCCO bank voltage | Notes |
---|---|---|---|---|---|---|
12 | HR | J1 | 50 | 24 | user (VCCIO_12) | supported voltages from 1.2V to 3.3V |
13 | HR | J1 | 50 | 24 | user (VCCIO_13) | supported voltages from 1.2V to 3.3V |
34 | HR | J2 | 50 | 24 | user (VCCIO_34) | supported voltages from 1.2V to 3.3V |
35 | HR | J2 | 50 | 24 | user (VCCIO_35) | supported voltages from 1.2V to 3.3V |
500 | MIO | J2 | 5 | - | 1.8V | - |
501 | MIO | J3 | 12 | - | 1.8V | - |
Table 2: B2B connector pin-outs of available PL and PS banks of the SoC module
For detailed information about the pin out, please refer to the Pin-out Table.
The B2B connector J1 and J2 provide also access to the MGT-banks of the SoC module. There are 8 high-speed data links (Xilinx GTX transceiver) available composed as differential signaling pairs for both directions (RX/TX), means from module to base-board and vice versa.
The MGT-banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT-lanes are available on the B2B connectors:
Bank | I/O signal count | LVDS-pairs count | MGT-lanes count (RX/TX LVDS-pairs) | bank's reference clock inputs (LVDS-pairs) | Notes |
---|---|---|---|---|---|
Bank 111 | 20 | 10 | 4 | 1 reference clock signal (MGT_CLK3) from programmable quad PLL clock generator U16 to bank's pins AA6/AA5. 1 reference clock signal (MGT_CLK2) from B2B connector J3 (pins J3-81/J3-83) to bank's pins W6/W5. | - |
Bank 112 | 20 | 10 | 4 | 1 reference clock signal (MGT_CLK1) from programmable quad PLL clock generator U16 to bank's pins U6/U5. 1 reference clock signal (MGT_CLK0) from B2B connector J3 (pins J3-75/J3-77) to bank's pins R6/R5. | - |
Table 3: B2B connector pin-outs of available MGT-lanes of the SoC module
The B2B connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:
Interfaces | I/O signal count | pin schematic names / B2B pins | connected with | Notes | |
---|---|---|---|---|---|
JTAG | 5 | TMS, pin J1-144 TDI, pin J1-142 TDO, pin J1-145 TCK, pin J1-143 JTAG_EN, pin J1-148 | SC CPLD, bank 0 |
At normal operation the JTAG-signals will be forwarded to the SoC module. Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG-interface. VCCIO: PS_3.3V | |
I²C | 2 | I2C_33_SCL, pin J2-119 I2C_33_SDA, pin J2-121 | RTC, U24 SC CPLD, U2 MAC Address EEPROM, U23 Zynq-module, U1 Quad programmable PLL clock generator, U16 | The I²C-interface of the RTC U24 (pin 12: SCL, pin 11: SDA) and the B2B-connector J2 are operating with the reference voltage PS_3.3V. Following component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17): SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL) MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA) Zynq-chip U1, bank 500 (MIO0), pins A25 (SCL), B26 (SDA) Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA) Component's I²C Addresses: RTC: 0x6F RTC RAM: 0x57 MAC Address EEPROM: 0x53 Quad programmable PLL clock generator: 0x70 | |
control lines | 5 | RST_IN_N, pin J2-131 | SC CPLD bank 0, pins 25; Reset Circuit U41, pin 3 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip. | |
PS_SRST, pin J2-152 | SC CPLD bank 2, pin 12; Zynq-chip bank 501, pin A22 | Low-active system-reset pin of Zynq-chip. | |||
BOOTMODE, pin J2-133 | Zynq-chip bank 500, pin F24 | Control line which sets in conjunction with signal 'BOOTMODE1' the boot source of the Zynq-chip. See section "Boot Modes". | |||
PWR_PL_OK, pin J2-135 | SC CPLD bank 0, pin 27; PG-signal DCDC-converter U8, pin 9 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. | |||
PWR_PS_OK, pin J2-139 | SC CPLD bank 0, pin 28; PG-signal DCDC-converter U31, pin 2 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. |
Table 4: B2B connector pin-outs of available interfaces
MIO | Function | connected with | Notes | MIO | Function | connected with | Notes | |
---|---|---|---|---|---|---|---|---|
0 | GPIO | J2-137, SC CPLD bank 2, pin 14 | user I/O on B2B | 16..27 | ETH0 | Ethernet PHY U7 | RGMII | |
1 | QSPI0 | QSPI Flash Memory U14, pin C2 | SPI Flash-CS | 28..39 | USB0 | USB PHY U32 | ULPI | |
2 | QSPI0 | QSPI Flash Memory U14, pin D3 | SPI Flash-DQ0 | 40 | GPIO | J2-150 | user I/O on B2B | |
3 | QSPI0 | QSPI Flash Memory U14, pin D2 | SPI Flash-DQ1 | 41 | GPIO | J2-152 | user I/O on B2B | |
4 | QSPI0 | QSPI Flash Memory U14, pin C4 | SPI Flash-DQ2 | 42 | GPIO | J2-154 | user I/O on B2B | |
5 | QSPI0 | QSPI Flash Memory U14, pin D4 | SPI Flash-DQ3 | 43 | GPIO | J2-156 | user I/O on B2B | |
6 | QSPI0 | QSPI Flash Memory U14, pin B2 | SPI Flash-SCK | 44 | GPIO | J2-158 | user I/O on B2B | |
7 | GPIO | USB PHY U32, pin 27 | USB PHY Reset | 45 | GPIO | J2-160 | user I/O on B2B | |
8 | GPIO | SC CPLD bank 2, pin 13 | user I/O | 46 | GPIO | J2-145 | user I/O on B2B | |
9 | GPIO | Ethernet PHY U7, pin 16 | Ethernet PHY Reset | 47 | GPIO | J2-147 | user I/O on B2B | |
10 | I²C | SCL-line I²C-interface | 1.8V ref. voltage | 48 | GPIO | J2-149 | user I/O on B2B | |
11 | I²C | SDA-line I²C-interface | 1.8V ref. voltage | 49 | GPIO | J2-151 | user I/O on B2B | |
12 | GPIO | J2-123 | user I/O on B2B | 50 | GPIO | J2-153 | user I/O on B2B | |
13 | GPIO | J2-125 | user I/O on B2B | 51 | GPIO | J2-155 | user I/O on B2B | |
14 | GPIO | J2-127 | user I/O on B2B | 52 | ETH0 | USB PHY U32, pin 7 | MDC | |
15 | GPIO | J2-129 | user I/O on B2B | 53 | ETH0 | USB PHY U32, pin 8 | MDIO |
Table 5: Default MIO Mapping
On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U9), the 125MHz output clock is available on B2B connector J2, pin J2-150.
PHY Pin | ZYNQ PS | B2B | Notes |
---|---|---|---|
MDC/MDIO | MIO52, MIO53 | - | - |
PHY LEDs | - | PHY_LED0: J2-144 | - |
PHY_LED2 / INTn: | - | J2-148 | low active interrupt line |
PHY_CLK125M | - | J2-150 | 125 MHz Ethernet PHY clock out |
CONFIG | - | - | permanent high (PS_1.8V) |
RESETn | MIO9 | - | low active reset line |
RGMII | MIO16..MIO27 | - | Reduced Gigabit Media Independent Interface |
SGMII | - | - | Serial Gigabit Media Independent Interface |
MDI | - | PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140 | Media Independent Interface |
Table 6: Ethernet PHY interface connections
A Microchip 24AA025E48 EEPROM (U23) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave address 0x53.
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).
PHY Pin | ZYNQ Pin | B2B Name | Notes |
---|---|---|---|
ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
REFCLK | - | - | 52MHz from on board oscillator (U33) |
REFSEL[0..2] | - | - | all pins set to GND selects the external reference clock frequency @52MHz |
RESETB | MIO7 | - | low-active reset line |
CLKOUT | MIO36 | - | set to VDDIO (1.8V) to select reference clock operation mode |
DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines |
CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active high enable signal |
VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics |
ID | - | OTG_ID, pin J2-143 | For an A-Device connect to ground, for a B-Device left floating |
Table 7: USB PHY interface connections
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD on bank 3, pin 4.
LED | Color | connected with | Description and Notes |
---|---|---|---|
D1 | Green | SC CPLD, bank 3, pin 5 | System main status LED. |
D2 | Red | Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9) | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC CPLD can not power up the PL supply voltage. |
Table 8: LEDs of the SoC module
The Zynq-module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO0 pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
Boot Mode | MIO5 (BOOTMODE_1) | MIO4 (BOOTMODE) | MIO3 | Note |
---|---|---|---|---|
JTAG | 0 | 0 | 0 | - |
NOR | 0 | 0 | 1 | MIO3 pin is not connected to QSPI Flash Memory |
NAND | 0 | 1 | 0 | - |
QSPI Flash Memory | 1 | 0 | 0 | standard mode in current configuration |
SD-Card | 1 | 1 | 0 | SD-Card on base board necessary |
Table 9: Selectable boot modes
The System Controller CPLD is the central system management unit on the SoC module which generates control signals and evaluates signals like the "Power Good" signals. Interfaces between the on-board peripherals and the SoC-module are by-passed, forwarded and controlled by the System Controller CPLD.
CPLD bank | CPLD bank's VCCIO |
---|---|
0 | 3.3V |
1 | 1.8V |
2 | 1.8V |
3 | 3.3V |
Table 10: VCCIO voltages of CPLD banks
Following table describes the interfaces and functionalities established by the System Controller CPLD:
CPLD functionality | interface | designated CPLD pins | connected with | Note |
---|---|---|---|---|
Table 11: System Controller CPLD functionalities
The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.
Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 MHz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25 MHz | U9 | - | - |
USB PHY reference | 52 MHz | U15 | - | - |
PLL reference | 25 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 MHz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
PLL connection
I/O | Default Frequency | Notes |
---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base board. |
IN3 | 25MHz | Fixed input clock. |
IN4 | - | - |
IN5/IN6 | 125MHz | Ethernet PHY output clock. |
CLK0 | - | Not used, disabled. |
CLK1 | - | Not used, disabled. |
CLK2 A/B | 125MHz | MGT reference clock 1. |
CLK3A | - | Bank 34 clock input, default disabled, User clock. |
CLK3B | - | Not used, disabled. |
TE0715-xx-30 has several HP banks on B2B connectors. Those banks have maximum voltage tolerance of 1.8V. Please check special instructions for the baseboard to be used with TE0715-xx-30. |
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
Power Input Pin | Max Current |
---|---|
VIN | TBD* |
3.3VIN | TBD* |
* TBD - To Be Determined soon with reference design setup.
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3W.
For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
Voltages on B2B Connectors | B2B JM1 Pin | B2B JM2-Pin | Input/ Output | Note |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage. |
3.3VIN | 13, 15 | - | Input | Supply voltage. |
VCCIO13 | 9, 11 | - | Input | High range bank voltage. |
VCCIO34 | - | 5 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
VCCIO35 | - | 7, 9 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
VBAT_IN | 79 | - | Input | RTC battery-buffer supply voltage. |
3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
1.8V | 39 | - | Output | Internal 1.8V voltage level. |
DDR_PWR | - | 19 | Output | Internal 1.5V or 1.35V voltage level, depends on revision. |
VREF_JTAG | 91 | Output | JTAG reference voltage (3.3V). |
Bank | Schematic Name | Voltage | TE0715-xx-15 | TE0715-xx-30 |
---|---|---|---|---|
500 | VCCO_MIO0_500 | 3.3V | - | - |
501 | VCCO_MIO1_501 | 1.8V | - | - |
502 | VCCO_DDR_502 | 1.5V | - | - |
0 Config | VCCO_0 | 3.3V | - | - |
13 HR | VCCO_13 | User | HR: 1.2V to 3.3V | HR: 1.2V to 3.3V |
34 HR/HP | VCCO_34 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
35 HR/HP | VCCO_35 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | - |
3.3VIN supply voltage | -0.4 | 3.6 | V | - |
VBAT supply voltage | -1 | 6.0 | V | - |
PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks. |
I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0715-xx-15 does not have HP banks. |
GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal. |
Storage temperature | -40 | +85 | °C | - |
Storage temperature without the ISL12020MIRZ | -55 | +100 | °C | - |
Assembly variants for higher storage temperature range are available on request. |
Please check Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Parameter | Min | Max | Units | Notes | Reference Document |
---|---|---|---|---|---|
VIN supply voltage | 2.5 | 5.5 | V | ||
3.3VIN supply voltage | 3.135 | 3.465 | V | ||
VBAT_IN supply voltage | 2.7 | 5.5 | V | ||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks | Xilinx datasheet DS191 |
I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 or DS187 |
I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks (*) Check datasheet | Xilinx datasheet DS191 |
Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
.. g - Plain module
.. g - Set of bolts and nuts
Date | Revision | Notes | Link to PCN | Documentation Link |
---|---|---|---|---|
2016-10-11 | 02 | Production release | TE0745-02 | |
2016-04-18 | 01 | Prototypes | TE0745-01 |
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Date | Revision | Contributors | Description |
---|---|---|---|
2017-02-05 | Jan Kumann | Initial document. |