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Table of Contents

Overview

Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0726 for downloadable version of this manual and additional technical documentation of the product.
 

The Trenz Electronic TE0726 "ZynqBerry" is a industrial-grade Raspberry Pi form-factor compatible FPGA SoM (System on Module) based on Xilinx Zynq-7010 SoC (XC7Z010 System on Chip) with up to 512 MByte DDR3L SDRAM, 4 x USB 2.0 ports, 10/100 Mbit Ethernet port and 16 MByte Flash memory. All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Block Diagram

Main Components

  1. Xilinx Zynq XC7Z010 All Programmable SoC, U1
  2. 512 MByte DDR3L SDRAM, U8
  3. Lattice Semiconductor MachXO2 System Controller CPLD, U11
  4. Dual high-speed USB to multipurpose UART/FIFO, U3
  5. 2 Kbit Microwire compatible serial EEPROM, U6
  6. Low-power, programmable oscillator @ 12.000000 MHz, U7
  7. Ultra-low capacitance double rail-to-rail ESD protection diode ,U4
  8. Micro-USB 2.0 B receptacle, J1
  9. Green LED (GLED), D1
  10. Red LED (RLED), D2
  11. DSI LCD connector, J4
  12. JTAGENB, when low, TDO, TDI, TMS and TCK function as GPIOs, J15
  13. Fiducial mark PM2
  14. External I2C bus with interrupt signal and power line, J2
  15. Low-voltage 4-channel I2C and SMBus multiplexer with interrupt logic, U10
  16. 2x20 pin 2.54 GPIO header, J8
  17. 128 Mbit (16 MByte) 3.0V SPI Flash memory, U5

  18. USB 2.0 Hub and 10/100 Ethernet controller, U2
  19. External reset
  20. 2 Kbit Microwire compatible serial EEPROM, U9
  21. PUDC of Zynq, active low enables  internal pull-ups during configuration on all SelectIO pins
  22. Dual USB A receptacle, J12. Also fiducial mark PM1
  23. Dual USB A receptacle, J11
  24. Low power programmable oscillator @ 25.000000 MHz, U13
  25. Molex’s miniature traceability S/N pad for low-cost, unique product identification
  26. RJ-45 Ethernet connector with 10/100 integrated magnetics, J10. Also fiducial mark PM3
  27. 3.5mm RCA audio jack, J7
  28. 1A PowerSoC synchronous buck regulator with integrated inductor (3.3V), U20
  29. 1A PowerSoC synchronous buck regulator with integrated inductor (1.8V), U19
  30. ZIF FFC/FPC CSI-2 camera connector, J3
  31. HDMI connector, J6
  32. Common mode filter with ESD protection, D8

  33. Common mode filter with ESD protection, D9

  34. 1A PowerSoC synchronous buck regulator with integrated inductor (1.35V), U16
  35. Additional external +5V power supply connector, J5
  36. Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18

  37. Low-power programmable oscillator @ 33.333333 MHz, U14
  38. Ultra-low supply current voltage monitor with optional watchdog, U22
  39. Fiducial mark PM4
  40. Micro SD memory card connector with detect switch, J9
  41. JTAG interface, TP1 (TDI), TP3 (TDO), TP5 (TCK), TP7 (TMS)
  42. 1A PowerSoC synchronous buck regulator with integrated inductor (1.0V), U17
  43. Fiducial mark PM6
  44. 0.5A dual channel current-limited power switch, U15
  45. 0.5A dual channel current-limited power switch, U21
  46. Fiducial mark PM5

Key Features

Initial Delivery State

Up on delivery from Trenz Electronic System Controller CPLD is programmed with the standard firmware and FTDI FT2232H EEPROM contains pre-programmed Digilent license needed by Xilinx software tools for JTAG access, all other programmable devices are empty.

Signals, Interfaces and Pins

Camera Serial Interface (CSI-2)

The TE0726-03 module has CSI-2 specification compatible serial camera interface routed from Zynq SoC bank 34 to the connector J3.

FPGA BankZynq PinSignal NameConnected To
34M10CSI_D0_PCSI-2 camera connector J3
34M11CSI_D0_NCSI-2 camera connector J3
34P13CSI_D1_PCSI-2 camera connector J3
34P14CSI_D1_NCSI-2 camera connector J3
34N11CSI_C_PCSI-2 camera connector J3
34N12CSI_C_NCSI-2 camera connector J3

Display Serial Interface (DSI)

The TE0726-03 module has MIPI Alliance DSI specification compatible serial display interface routed from Zynq SoC bank 35 to the connector J4.

FPGA BankZynq PinSignal NameConnected To
35F13DSI_D0_R_NDSI display connector J4
35F14DSI_D0_R_PDSI display connector J4
35F12DSI_D1_R_NDSI display connector J4
35E13DSI_D1_R_PDSI display connector J4
35E11DSI_C_R_NDSI display connector J4
35E12DSI_C_R_PDSI display connector J4

See also section FPGA IO Banks Pin Mapping, pins DSI_XA and DSI_XB.

HDMI Interface

HDMI interface is routed from Zynq SoC bank 34 to the external connector J6 via EMI4192 ESD protector/EMI filters.

FPGA BankZynq PinSignal NameConnected To
 34K12CEC_BHDMI connector J6
34P8HDMI_TX0_NHDMI connector J6 via EMI filter/ESD protector
34P9HDMI_TX0_PHDMI connector J6 via EMI filter/ESD protector
34R10HDMI_TX1_NHDMI connector J6 via EMI filter/ESD protector
34P10HDMI_TX1_PHDMI connector J6 via EMI filter/ESD protector
34R11HDMI_TX2_NHDMI connector J6 via EMI filter/ESD protector
34P11HDMI_TX2_PHDMI connector J6 via EMI filter/ESD protector
34R7HDMI_TXC_NHDMI connector J6 via EMI filter/ESD protector
34R8HDMI_TXC_PHDMI connector J6 via EMI filter/ESD protector

Audio Output

Pulse-width modulated stereo audio output is routed from Zynq SoC bank 34 to external 3.5mm socket J7.

FPGA BankZynq PinSignal NameConnected To
34N7PWM_L3.5mm stereo socket J7
34N8PWM_R3.5mm stereo socket J7

SD Card Socket

Micro SD memory card connector J9 with detect switch is connected to the Zynq Soc PS MIO bank 500. See also section Default MIO Mapping.

FPGA IO Banks Pin Mapping

BankZynq PinNameConnected To
34G14PUDCJumper J14
35G15DSI_XASystem Controller CPLD, pin 16
35F15DSI_XBSystem Controller CPLD, pin 17

GPIO to Header J8 Interface Mapping

GPIOZynq PinJ8 Pin GPIOZynq PinJ8 Pin
GPIO2K153 GPIO15N1310
GPIO3J145 GPIO16L1336
GPIO4H127 GPIO17G1111
GPIO5N1429 GPIO18H1112
GPIO6R1531 GPIO19R1235
GPIO7L1426 GPIO20M1438
GPIO8L1524 GPIO21P1540
GPIO9J1321 GPIO22H1315
GPIO19H1419 GPIO23J1116
GPIO11J1523 GPIO24K1118
GPIO12M1532 GPIO25K1322
GPIO13R1333 GPIO26L1237
GPIO14M128 GPIO27G1213


Default MIO Mapping

Bank 500 MIOs

MIO

FunctionNotes
0

MIO0_INT

Interrupt signal from I2C MUX.
1SPI0_CSSPI chip select.
2SPI0_DQ0/M0Bi-directional data line 0
3SPI0_DQ1/M1Bi-directional data line 1
4SPI0_DQ2/M2Bi-directional data line 2
5SPI0_DQ3/M3Bi-directional data line 3
6SPI0_SCKSPI clock.
7MIO7RESETB of USB3320 chip, U18
8MIO8System Controller CPLD pin 28
9MIO9System Controller CPLD pin 29
10SD_D0Serial data 0.
11SD_CMDCommand/Response.
12SD_CLKSerial clock.
13SD_D1Serial data 1.
14SD_D2Serial data 2.
15SD_D3Serial data 3.


Bank 501 MIOs

 MIOFunctionNotes
28OTG-DATA4ULPI bi-directional data bus.
29OTG-DIRData bus direction control signal.
30OTG-STPData throttle signal.
31OTG-NXTData stream stop.
32OTG-DATA0ULPI bi-directional data bus.
33OTG-DATA1ULPI bi-directional data bus.
34OTG-DATA2ULPI bi-directional data bus.
35OTG-DATA3ULPI bi-directional data bus.
36OTG-CLKULPI clock.
37OTG-DATA5ULPI bi-directional data bus.
38OTG-DATA6ULPI bi-directional data bus.
39OTG-DATA7ULPI bi-directional data bus.
48MUX_SCLI2C clock to I2C MUX.
49MUX_SDAI2C data to/from I2C MUX.
52MIO52System Controller CPLD pin 20
53MIO53System Controller CPLD pin 21

LED's

There are two LEDs on TE0726 module:

LED

Signal Name

Color

CPLD Pin

Notes

D1GLEDGreen5CPLD bank 3.

D2

RLED

Red

4

CPLD bank 3.

On-board Peripherals

System Controller CPLD

There is a System Controller CPLD chip LCMXO2-256HC from Lattice Semiconductor on-board. Refer to the TE0726 CPLD for more information.

Clocking

Signal Name

Clock IC

Default Frequency

Destination IC

Pin

Notes

PS_CLKU14

33.333333 MHz

U1

C7

Zynq SoC system reference clock.
OSCIU7

12.000000 MHz

U3

3

FT2232H oscillator input.

CLK24MU224 MHz (see also REFSEL0 .. 2)U1826Reference input/output clock, see datasheet.
CLK25MU1325.000000 MHzU261External 25 MHz crystal input.

Hi-speed USB 2.0 and 10/100 Mbit Ethernet

The TE0726-03 has on-board SMSC LAN9514 controller featuring USB 2.0 hub and 10/100 Mbit Ethernet controller. USB hub has four downstream ports and one upstream port, fully compliant with Universal Serial Bus Specification Revision 2.0. HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible. Upstream port is connected to the SMSC USB3320 hi-speed USB 2.0 ULPI transceiver which has full support for the optional On-The-Go (OTG) protocol.

High-Performance 10/100 Ethernet controller integrated into the same LAN9514 IC is fully compliant with IEEE802.3/802.3u standards, has integrated Ethernet MAC and PHY and supports both 10BASE-T and 100BASE-TX media.

256-byte EEPROM is connected via Microwire to the LAN9514 chip to store MAC address.

USB to JTAG/UART

The TE0726-03 has on-board high-speed USB 2.0 to UART/FIFO FT2232H controller from FTDI with external connection to micro-USB connector J1. There is also a 256-byte EEPROM wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools.

 

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

4-Channel I2C Multiplexer

Zynq MIO pin 48 (MUX_SCL) and pin 49 (MUX_SDA) are connected to the 4-channel I2C multiplexer chip TCA9544A from Texas Instruments having I2C address of 0x70. It has four slave I2C channels which are routed as follows:

ChannelConnected To
0Connector J8, pin 27 (ID_SDA) and pin 28 (ID_SCL).
1DSI connector J4, pin 12 (DSI_SDA) and pin 11 (DSI_SCL).
2HDMI connector J6, pin 16 (SDA) and pin 15 (SCL).
3CSI-2 camera connector J3, pin 14 (CSI_SDA) and pin 13 (CSI_SCL).

Each slave channel of TCA9544A has its own dedicated interrupt signal in order for the master to detect an interrupt on the INT output pin that can result from any of the slave devices connected to the INT0-INT3 input pins.

Boot Process

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader.

At least FSBL must be loaded from on-board SPI Flash, later all boot process can continue from SD Card. The easiest solution is to let FSBL to load bitstream and u-boot from SPI Flash, and then let u-boot to load Linux or any other OS image from SD Card.


Power and Power-On Sequence

To power-up a module, 5.0V power supply with minimum current capability of 1A is recommended.

Power Supply

TE0726 needs one single power source via micro-USB jack J1. However it is recommended to not use any USB equipment below USB standard 2.0 to power the module. Also two-pin header J5 can be used to provide power source if needed.

Power-On Sequence

There is no specific power-on sequence.

Power Rails and Bank Voltages

Rail/Bank

Name

Voltage

Notes

VCCINTVCCINT1.0VPL internal supply voltage.
VCCPINTVCCPINT1.0VPS internal logic supply voltage.
VCCPLLVCCPLL1.8VPS PLL supply.
VCCBATT_0VCCBATT_01.8V 
VCCAUXVCCAUX1.8VPL auxiliary supply voltage.
VCCPAUXVCCPAUX1.8VPS auxiliary supply voltage.
VCCADC_0VCCADC_01.8V 
RSVDVCC1..3RSVDVCC1..33.3V 
0VCCO_03.3VConfiguration bank.

34

VCCO_34

3.3V

PL HR I/O bank.
35VCCO_35

1.8V

PL HR I/O bank.

500VCC_MIO_5003.3VPS MIO bank.
501VCC_MIO_5013.3VPS MIO bank.

502

VCCO_DDR_502

1.35V

DDR3L SDRAM power-supply.

Variants Currently in Production

 TE0726 VariantZynq SoC

RAM

FlashEthernetTemperature Range
TE0726-03RXC7Z010-1CLG225C128 MByte16 MByte-Commercial grade
TE0726-03MXC7Z010-1CLG225C512 MByte16 MByte10/100 MbitCommercial grade
TE0726-03-07S-1CXC7Z007S-1CLG225C512 MByte16 MByte10/100 MbitCommercial grade

Technical Specifications

If TE0726 module is powered by micro-USB connector J1 VBUS pin, which voltage level is controlled by supplying host according to the USB standards and should be 5V, there is not much user can control here if using standard USB equipment. However, user can also power the module by applying voltage to the J5 connector from other external sources. In both cases following maximum voltage ratings apply.

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

Power supply voltage

J1: USB_V_BUS

J5: 5V

2.7

6.5

V

See AP2152SG-13 datasheet. Not applicable if TE0726 module is powered by micro-USB connector J1 as VBUS pin voltage level of 5V is controlled by the supplying side equipment.
VOUT of AP2152SG-13-VIN + 0.3VOutput voltage.
ILOAD of AP2152SG-13-Internal limitedAMaximum continuous load current.
PS MIO input voltage-0.4VCCO_MIO + 0.55VVCCO_MIO0_500 and VCCO_MIO1_501.
PL Bank 34 I/O input voltage-0.4VCCO_34 + 0.55V 
PL Bank 35 I/O input voltage-0.4VCCO_35 + 0.55V 

Storage temperature

-55

+125

°C

-

See also the Xilinx datasheet DS187 for more information about absolute maximum ratings.

Recommended Operating Conditions

ParameterMinMaxUnitsNotes
Power supply voltage

2.7

5.5VSee AP2152SG-13 and EN5311QI datasheets.
IOUT of AP2152SG-130500mA 
PS MIO input voltage-0.2VCCO_MIO + 0.2VVCCO_MIO0_500 and VCCO_MIO1_501.
PL Bank 34 I/O input voltage-0.2VCCO_34 + 0.2V 
PL Bank 35 I/O input voltage-0.2VCCO_35 + 0.2V 
Operating temperature070

°C

See LAN9514 datasheet.

The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Physical Dimensions

All dimensions are shown in millimeters. Additional sketches, drawings and schematics can be found here.

Weight

VariantWeight in gNote
TE0726-03M---Plain module.
TE0726-03R---Plain module.
TE0726-03-07S-1C---Plain module.

Revision History

Hardware Revision History

DateRevision

Notes

PCN LinkDocumentation Link
2016-05-0603--TE0726-03
2016-01-2602--TE0726-02
 -

01

-

- 

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

 

Document Change History

Date

Revision

Contributors

Description

2017-05-24
Jan Kumann

Absolute maximum ratings.

Layout redesign.

2017-05-24

V.2

John HartfielWeight.

2017-05-24

V.1

Jan Kumann

Initial version.

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